Datasheet

Rev. D | Page 38 of 56 | April 2013
ADSP-21371/ADSP-21375
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 31. IDP
signals are routed to the DAI_P20–1 pins using the SRU. There-
fore, the timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 31. Input Data Port (IDP)
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
SISFS
1
Frame Sync Setup Before Serial Clock Rising Edge 4.95 3.8 ns
t
SIHFS
1
Frame Sync Hold After Serial Clock Rising Edge 2.5 2.5 ns
t
SISD
1
Data Setup Before Serial Clock Rising Edge 3.35 2.5 ns
t
SIHD
1
Data Hold After Serial Clock Rising Edge 2.5 2.5 ns
t
IDPCLKW
Clock Width (t
PCLK
× 4) ÷ 2 – 1 (t
PCLK
× 4) ÷ 2 – 1 ns
t
IDPCLK
Clock Period t
PCLK
× 4 t
PCLK
× 4 ns
1
The data, serial clock, and frame sync signals can come from any of the DAI pins. Serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be either
CLKIN or any of the DAI pins.
Figure 23. IDP Master Timing
DAI_P20–1
(SCLK)
SAMPLE EDGE
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
t
IDPCLK
t
IDPCLKW
t
SISFS
t
SIHFS
t
SIHD
t
SISD