Datasheet

ADSP-21371/ADSP-21375
Rev. D | Page 37 of 56 | April 2013
Table 30. Serial Ports—External Late Frame Sync
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Switching Characteristics
t
DDTLFSE
1
Data Delay from Late External Transmit Frame Sync
or External Receive Frame Sync with
MCE = 1, MFD = 0
12.7 10 ns
t
DDTENFS
1
Data Enable for MCE = 1, MFD = 0 0.5 0.5 ns
1
The t
DDTLFSE
and t
DDTENFS
parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.
Figure 22. External Late Frame Sync
1
1
This figure reflects changes made to support left-justified sample pair mode.
DRIVE SAMPLE
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
2ND BIT
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL
A/B)
1ST BIT
DRIVE
t
DDTE/I
t
HDTE/I
t
DDTLFSE
t
DDTENFS
t
SFSE/I
DRIVE SAMPLE
LATE EXTERNAL TRANSMIT FS
2ND BIT
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL
A/B)
1ST BIT
DRIVE
t
DDTE/I
t
HDTE/I
t
DDTLFSE
t
DDTENFS
t
SFSE/I
t
HFSE/I
t
HFSE/I