Datasheet

Rev. D | Page 34 of 56 | April 2013
ADSP-21371/ADSP-21375
Table 28. Serial Ports—Internal Clock
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
SFSI
1
Frame Sync Setup Before SCLK (Externally Generated Frame
Sync in either Transmit or Receive Mode) 7 7 ns
t
HFSI
1
Frame Sync Hold After SCLK (Externally Generated Frame Sync
in either Transmit or Receive Mode) 2.5 2.5 ns
t
SDRI
1
Receive Data Setup Before SCLK 7 7 ns
t
HDRI
1
Receive Data Hold After SCLK 2.5 2.5 ns
Switching Characteristics
t
DFSI
2
Frame Sync Delay After SCLK (Internally Generated Frame Sync
in Transmit Mode)
44ns
t
HOFSI
2
Frame Sync Hold After SCLK (Internally Generated Frame Sync
in Transmit Mode)
–1.0 –1.0 ns
t
DFSIR
2
Frame Sync Delay After SCLK (Internally Generated Frame Sync
in Receive Mode)
13.5 10.7 ns
t
HOFSIR
2
Frame Sync Hold After SCLK (Internally Generated Frame Sync
in Receive Mode)
–1.0 –1.0 ns
t
DDTI
2
Transmit Data Delay After SCLK 4.6 3.6 ns
t
HDTI
2
Transmit Data Hold After SCLK –1.0 –1.0 ns
t
SCKLIW
3
Transmit or Receive SCLK Width 2 × t
PCLK
– 1.5 2 × t
PCLK
+ 1.5 2 × t
PCLK
– 1.5 2 × t
PCLK
+ 1.5 ns
1
Referenced to the sample edge.
2
Referenced to drive edge.
3
Minimum SPORT divisor register value.