Datasheet

ADSP-21371/ADSP-21375
Rev. D | Page 33 of 56 | April 2013
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) serial clock
(SCLK) width.
Serial port signals are routed to the DAI_P20–1 pins using the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 27. Serial Ports—External Clock
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
SFSE
1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in either Transmit
or Receive Mode)
2.8 2.5 ns
t
HFSE
1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in either Transmit
or Receive Mode)
2.5 2.5 ns
t
SDRE
1
Receive Data Setup Before Receive SCLK 3.1 2.5 ns
t
HDRE
1
Receive Data Hold After SCLK 2.5 2.5 ns
t
SCLKW
SCLK Width (t
PCLK
× 4) ÷ 2 – 1.5 (t
PCLK
× 4) ÷ 2 – 1.5 ns
t
SCLK
SCLK Period t
PCLK
× 4 t
PCLK
× 4 ns
Switching Characteristics
t
DFSE
2
Frame Sync Delay After SCLK (Internally Generated
Frame Sync in either Transmit or Receive Mode) 13.5 10.5 ns
t
HOFSE
2
Frame Sync Hold After SCLK (Internally Generated
Frame Sync in either Transmit or Receive Mode) 2 2 ns
t
DDTE
2
Transmit Data Delay After Transmit SCLK 13.9 11 ns
t
HDTE
2
Transmit Data Hold After Transmit SCLK 2 2 ns
1
Referenced to sample edge.
2
Referenced to drive edge.