Datasheet

ADSP-21371/ADSP-21375
Rev. D | Page 31 of 56 | April 2013
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for ACK, DATA, RD
, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 26. Memory Write—Bus Master
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
DAAK
ACK Delay from Address, Selects
1, 2
t
SDCLK
– 11 + W t
SDCLK
– 10.1 + W ns
t
DSAK
ACK Delay from WR Low
1, 3
W – 7.35 W – 7.1 ns
Switching Characteristics
t
DAWH
Address, Selects to WR Deasserted
2
t
SDCLK
–4.3 + W t
SDCLK
–3.6 + W ns
t
DAWL
Address, Selects to WR Low
2
t
SDCLK
– 2.7 t
SDCLK
– 2.7 ns
t
WW
WR Pulse Width W – 1.3 W – 1.3 ns
t
DDWH
Data Setup Before WR High t
SDCLK
– 3.0 + W t
SDCLK
– 3.0 + W ns
t
DWHA
Address Hold After WR Deasserted H + 0.15 H + 0.15 ns
t
DWHD
Data Hold After WR Deasserted H + 0.02 H + 0.02 ns
t
DATRWH
Data Disable After WR Deasserted
4
t
SDCLK
– 1.37 + H t
SDCLK
+ 10.7+ H t
SDCLK
– 1.37 + H t
SDCLK
+ 4.9+ H ns
t
WWR
WR High to WR, RD Low t
SDCLK
– 1.5+ H t
SDCLK
– 1.5+ H ns
t
DDWR
Data Disable Before RD Low 2t
SDCLK
– 12 2t
SDCLK
– 5.1 ns
t
WDE
WR Low to Data Enabled t
SDCLK
– 4.1 t
SDCLK
– 4.1 ns
W = (number of wait states specified in AMICTLx register) × t
SDCLK
, H = (number of hold cycles specified in AMICTLx register) × t
SDCLK
1
ACK delay/setup: System must meet t
DAAK
, or t
DSAK
, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t
DAAK
or t
DSAK
.
2
The falling edge of MSx is referenced.
3
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
4
See Test Conditions on Page 49 for calculation of hold times given capacitive and dc loads.