Datasheet

ADSP-21371/ADSP-21375
Rev. D | Page 29 of 56 | April 2013
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for ACK, DATA, RD
, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 25. Memory Read—Bus Master
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
DAD
Address, Selects Delay to Data Valid
1, 2, 3
W + t
SDCLK
– 5.12 W + t
SDCLK
– 5.12 ns
t
DRLD
RD Low to Data Valid
1, 3
W – 3 W – 3 ns
t
SDS
Data Setup to RD High 2.2 2.2 ns
t
HDRH
Data Hold from RD High
4, 5
00ns
t
DAAK
ACK Delay from Address, Selects
2, 6
t
SCDCLK
– 11.4 + W t
SCDCLK
– 10.1 + W ns
t
DSAK
ACK Delay from RD Low
5
W – 7.25 W – 7.0 ns
Switching Characteristics
t
DRHA
Address Selects Hold After RD High RHC + 0.38 RHC + 0.38 ns
t
DARL
Address Selects to RD Low
2
t
SDCLK
– 3.8 t
SDCLK
– 3.3 ns
t
RW
RD Pulse Width W – 1.4 W – 1.4 ns
t
RWR
RD High to WR, RD, Low HI + t
SDCLK
– 0.8 HI + t
SDCLK
– 0.8 ns
W = (number of wait states specified in AMICTLx register) × t
SDCLK
HI = RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) × t
SDCLK
IC = (number of idle cycles specified in AMICTLx register) × t
SDCLK
)
H = (number of hold cycles specified in AMICTLx register) × t
SDCLK
1
Data delay/setup: System must meet t
DAD
, t
DRLD
, or t
SDS.
2
The falling edge of MSx, is referenced.
3
The maximum limit of timing requirement values for t
DAD
and t
DRLD
parameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not
used.
4
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.
5
Data hold: User must meet t
HDRH
in asynchronous access mode. See Test Conditions on Page 49 for the calculation of hold times given capacitive and dc loads.
6
ACK delay/setup: User must meet t
DAAK
, or t
DSAK
, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t
DAAK
or t
DSAK
.