Datasheet

Rev. D | Page 28 of 56 | April 2013
ADSP-21371/ADSP-21375
SDRAM Interface Timing
Maximum SDRAM frequency for 1.2 V is 133 MHz SDCLK.
Table 24. SDRAM Interface Timing
1
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
SSDAT
DATA Setup Before SDCLK 0.58 0.58 ns
t
HSDAT
DATA Hold After SDCLK 2.2 2.2 ns
Switching Characteristics
t
SDCLK
SDCLK Period 10 7.5 ns
t
SDCLKH
SDCLK Width High43ns
t
SDCLKL
SDCLK Width Low 43ns
t
DCAD
Command, ADDR, Data Delay After SDCLK
2
6.4 5.3 ns
t
HCAD
Command, ADDR, Data Hold After SDCLK
2
1.3 1.3 ns
t
DSDAT
Data Disable After SDCLK 5.3 5.3 ns
t
ENSDAT
Data Enable After SDCLK 1.6 1.6 ns
1
For F
CCLK
= 133 MHz (SDCLK ratio = 1:2).
2
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, and SDCKE.
Figure 17. SDRAM Interface Timing for 133 MHz SDCLK
SDCLK
DATA (IN)
DATA (OUT)
COMMAND/ADDR
(OUT)
t
SDCLKH
t
SDCLKL
t
HSDAT
t
SSDAT
t
HCAD
t
DCAD
t
ENSDAT
t
DCAD
t
DSDAT
t
HCAD
t
SDCLK