Datasheet

Rev. D | Page 26 of 56 | April 2013
ADSP-21371/ADSP-21375
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing param-
eters and switching characteristics apply to external DAI pins
(DAI_P01 through DAI_P20).
Table 22. Precision Clock Generator (Direct Pin Routing)
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
PCGIP
Input Clock Period t
PCLK
× 4 t
PCLK
× 4 ns
t
STRIG
PCG Trigger Setup Before
Falling Edge of PCG Input Clock
4.5 4.5 ns
t
HTRIG
PCG Trigger Hold After Falling
Edge of PCG Input Clock
33ns
Switching Characteristics
t
DPCGIO
PCG Output Clock and Frame
Sync Active Edge Delay After
PCG Input Clock
2.5 12.8 2.5 10 ns
t
DTRIGCLK
PCG Output Clock Delay After
PCG Trigger
2.5 + ((2.5) × t
PCGIW
) 12.8 + ((2.5) × t
PCGIW
) 2.5 + ((2.5) × t
PCGIW
) 10 + ((2.5) × t
PCGIW
)ns
t
DTRIGFS
PCG Frame Sync Delay After
PCG Trigger
2.5 + ((2.5 + D – PH)
× t
PCGIW
)
12.8 + ((2.5 + D – PH)
× t
PCGIW
)
2.5 + ((2.5 + D – PH)
× t
PCGIW
)
10 + ((2.5 + D – PH)
× t
PCGIW
)
ns
t
PCGOW
1
Output Clock Period 2 × t
PCGIW
– 1 2 × t
PCGIW
– 1 ns
D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2137x SHARC Processor Hardware Reference, “Precision Clock Generators” chapter.
1
Normal mode of operation.
Figure 15. Precision Clock Generator (Direct Pin Routing)
DAI_Pn
DPI_Pn
PCG_TRIGx_I
DAI_Pm
DPI_Pm
PCG_EXTx_I
(CLKIN)
DAI_Py
DPI_Py
PCG_CLKx_O
DAI_Pz
DPI_Pz
PCG_FSx_O
t
DTRIGFS
t
DTRIGCLK
t
DPCGIO
t
STRIG
t
HTRIG
t
PCGOW
t
DPCGIO
t
PCGIP