Datasheet

Rev. D | Page 24 of 56 | April 2013
ADSP-21371/ADSP-21375
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer0 and
Timer1 in PWM_OUT (pulse-width modulation) mode. Timer
signals are routed to the DPI_P14–1 pins through the DPI SRU.
Therefore, the specifications provided below are valid at the
DPI_P14–1 pins.
Timer WDTH_CAP Timing
The following timing specification applies to Timer0 and
Timer1 in WDTH_CAP (pulse width count and capture) mode.
Timer signals are routed to the DPI_P14–1 pins through the
SRU. Therefore, the specifications provided below are valid at
the DPI_P14–1 pins.
Table 19. Timer PWM_OUT Timing
Parameter Min Max Unit
Switching Characteristic
t
PWMO
Timer Pulse Width Output 2 × t
PCLK
– 2 2 × (2
31
– 1) × t
PCLK
ns
Figure 12. Timer PWM_OUT Timing
PWM
OUTPUTS
t
PWMO
Table 20. Timer Width Capture Timing
Parameter Min Max Unit
Timing Requirement
t
PWI
Timer Pulse Width 2 × t
PCLK
2 × (2
31
– 1) × t
PCLK
ns
Figure 13. Timer Width Capture Timing
TIMER
CAPTURE
INPUTS
t
PWI