Datasheet

ADSP-21371/ADSP-21375
Rev. D | Page 21 of 56 | April 2013
Clock Input
Clock Signals
The processor can use an external clock or a crystal. See the
CLKIN pin description in Table 9. Programs can configure the
processor to use its internal clock generator by connecting the
necessary components to CLKIN and XTAL. Figure 7 shows the
component connections used for a crystal operating in funda-
mental mode. Note that the clock rate is achieved using a
16.67 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve
the full core clock rate, programs need to configure the multi-
plier bits in the PMCTL register.
Table 14. Clock Input
Parameter
200 MHz 266 MHz
Unit
Min Max Min Max
Timing Requirements
t
CK
CLKIN Period 30
1
1
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in the PMCTL register.
100 22.5
1
100 ns
t
CKL
CLKIN Width Low 15
1
45 11.25
1
45 ns
t
CKH
CLKIN Width High 15
1
45 11.25
1
45 ns
t
CKRF
CLKIN Rise/Fall (0.4 V to 2.0 V) 6 6 ns
t
CCLK
2
2
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CCLK
.
CCLK Period 5 103.7510ns
f
VCO
VCO Frequency 200 800 200 800 MHz
Figure 6. Clock Input
CLKIN
t
CK
t
CKL
t
CKH
Figure 7. 266 MHz Operation (Fundamental Mode Crystal)
C1
22pF
Y1
R1
1M⍀*
XTAL
CLKIN
C2
22pF
16.67 MHz
R2
47⍀*
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’SSPECIFICATIONS
*TYPICAL VALUES
ADSP-2137x