Datasheet

Rev. D | Page 2 of 56 | April 2013
ADSP-21371/ADSP-21375
TABLE OF CONTENTS
Summary ............................................................... 1
Dedicated Audio Components ................................. 1
General Description ................................................. 3
SHARC Family Core Architecture ............................ 4
Family Peripheral Architecture ................................ 6
I/O Processor Features ......................................... 10
System Design .................................................... 10
Development Tools ............................................. 11
Additional Information ........................................ 12
Related Signal Chains .......................................... 12
Pin Function Descriptions ....................................... 13
ADSP-21371/ADSP-21375 Specifications .................... 16
Operating Conditions .......................................... 16
Electrical Characteristics ....................................... 17
Package Information ............................................ 18
Maximum Power Dissipation ................................. 18
Absolute Maximum Ratings ................................... 18
ESD Sensitivity ................................................... 18
Timing Specifications ........................................... 18
Output Drive Currents ......................................... 49
Test Conditions .................................................. 49
Capacitive Loading .............................................. 49
Thermal Characteristics ........................................ 50
208-Lead LQFP_EP Pinout ....................................... 51
Package Dimensions ............................................... 55
Automotive Products .............................................. 56
Ordering Guide ..................................................... 56
REVISION HISTORY
4/13—Rev. C to Rev. D
Corrected Extended Precision Normal or Instruction Word
(48 bits) ADSP-21375 Internal Memory Space .................7
Updated Development Tools ..................................... 11
Added section Related Signal Chains ...........................12
Revised MS
1-0
pin description in
Pin Function Descriptions ........................................ 13
Corrected EMU
pin Type from O/T (pu) to O (O/D) (pu) in
Pin Function Descriptions ........................................ 13
Corrected T
JUNCTION
specifications in
Operating Conditions .............................................. 16
Added footnote 3 to Table 25 in
Memory Read—Bus Master .......................................29
Updated Serial Ports timing parameter data in Serial Ports—
External Clock ....................................................... 33
Updated Serial Ports timing parameter data in Serial Ports—
Internal Clock ........................................................ 34
Changed Max values in Table 33 in Pulse-Width Modulation
Generators (PWM) ................................................. 40
Updated timing parameters in Table 37 and in Figure 31 in
SPI Interface—Master .............................................. 44
Added 1.0 V, 200 MHz specifications to the following timing
specifications.
Clock Input ............................................................21
Precision Clock Generator (Direct Pin Routing) .............26
SDRAM Interface Timing ..........................................28
Memory Read—Bus Master .......................................29
Memory Write—Bus Master ......................................31
Serial Ports ............................................................33
Input Data Port (IDP) ..............................................38
S/PDIF Transmitter Input Data Timing ........................42
S/PDIF Receiver ......................................................43
SPI Interface—Slave .................................................45