Datasheet

ADSP-21371/ADSP-21375
Rev. D | Page 19 of 56 | April 2013
Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
f
VCO
specified in Table 14.
• The product of CLKIN and PLLM must never exceed 1/2
f
VCO
(max) in Table 14 if the input divider is not enabled
(INDIV = 0).
• The product of CLKIN and PLLM must never exceed f
VCO
(max) in Table 14 if the input divider is enabled
(INDIV = 1).
The VCO frequency is calculated as follows:
f
VCO
= 2 × PLLM × f
INPUT
f
CCLK
= (2 × PLLM × f
INPUT
)  (2 × PLLD)
where:
f
VCO
= VCO output
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = 1, 2, 4, 8 based on the PLLD value programmed on the
PMCTL register. During reset this value is 1.
f
INPUT
= Input frequency to the PLL.
f
INPUT
= CLKIN when the input divider is disabled or
f
INPUT
= CLKIN  2 when the input divider is enabled
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in Table 12. All
of the timing specifications for the ADSP-2137x peripherals are
defined in relation to t
PCLK
. See the peripheral specific section
for each peripheral’s timing information.
Figure 4 shows core to CLKIN relationships with external oscil-
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-2137x SHARC Processor Hard-
ware Reference.
Table 12. Clock Periods
Timing
Requirements Description
t
CK
CLKIN Clock Period
t
CCLK
Processor Core Clock Period
t
PCLK
Peripheral Clock Period = 2 × t
CCLK
Figure 4. Core Clock and System Clock Relationship to CLKIN
LOOP
FILTER
CLKIN
PCLK
SDCLK
SDRAM
DIVIDER
PMCTL
(PLLBP)
B
Y
P
A
S
S
M
U
X
DIVIDE
BY 2
PMCTL
(SDCKR)
CCLK
B
YP
A
S
S
M
U
X
PLL
XTAL
CLKIN
DIVIDER
RESETOUT
RESET
PLL
MULTIPLIER
BUF
VCO
BUF
PMCTL
(INDIV)
PLL
DIVIDER
CLK_CFGx/PMCTL (2xPLLM)
PI
N
M
U
X
RESETOUT
CLKOUT (TEST ONLY)
DELAY OF
4096 CLKIN
CYCLES
CORERST
CCLK
PCLK
PMCTL
(PLLBP)
PMCTL
(2xPLLD)
f
VCO
f
CCLK
f
INPUT