Datasheet

ADSP-21371/ADSP-21375
Rev. D | Page 15 of 56 | April 2013
RESET I Processor Reset. Resets the processor to a known state. Upon deassertion, there is a
4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET
input must be asserted
(low) at power-up.
XTAL O
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.
CLKIN I
Local Clock In. Used in conjunction with XTAL. CLKIN is the processor clock input. It
configures the processor to use either its internal clock generator or an external clock
source. Connecting the necessary components to CLKIN and XTAL enables the internal
clock generator. Connecting the external clock to CLKIN while leaving XTAL uncon-
nected configures the processor to use the external clock source such as an external
clock oscillator. CLKIN may not be halted, changed, or operated below the specified
frequency.
RESETOUT
/
RUNRSTIN
I/O (pu) Reset Out/Running Reset In. The default setting is reset out. This pin also has a second
function as RUNRSTIN, which is enabled by setting bit 0 of the RUNRSTCTL register. For
more information, see the ADSP-2137x SHARC Processor Hardware Reference .
1
Pull-up can be enabled/disabled, value of pull-up cannot be programmed.
Table 9. Pin Descriptions (Continued)
Name Type
State During
and After
Reset Description