Datasheet

Rev. D | Page 14 of 56 | April 2013
ADSP-21371/ADSP-21375
SDCKE O/T (pu) Pulled high/
driven high
SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK
signal. For details, see the data sheet supplied with the SDRAM device.
SDA10 O/T (pu) Pulled high/
driven low
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a non-
SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.
SDCLK O/T High-Z/driving SDRAM Clock.
MS
0–1
O/T (pu) Pulled high/
driven high
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-
sponding banks of external memory. The MS
1-0
lines are decoded memory address lines
that change at the same time as the other address lines. The MS1
pin can be used in
EPORT/FLASH boot mode. For more information, see the ADSP-2137x SHARC Processor
Hardware Reference.
FLAG[0]/IRQ0 I/O FLAG[0] INPUT FLAG0/Interrupt Request0.
FLAG[1]/IRQ1 I/O FLAG[1] INPUT FLAG1/Interrupt Request1.
FLAG[2]/IRQ2/
MS2
I/O with
programmable pu
(for MS mode)
FLAG[2] INPUT FLAG2/Interrupt Request/Memory Select2.
FLAG[3]/
TMREXP/ MS3
I/O with
programmable pu
(for MS mode)
FLAG[3] INPUT FLAG3/Timer Expired/Memory Select3.
TDI I (pu) Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 k  internal pull-up resistor.
TDO O/T
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TMS I (pu)
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 k 
internal pull-up resistor.
TCK I
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the processor.
TRST
I (pu) Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the processor. TRST
has a 22.5 k 
internal pull-up resistor.
EMU
O (O/D) (pu) Emulation Status. Must be connected to the processor. Analog Devices DSP Tools
product line of JTAG emulators target board connector only. EMU
has a 22.5 k  internal
pull-up resistor.
CLK_CFG
1–0
I Core to CLKIN Ratio Control. These pins set the start up clock frequency. See the
ADSP-2137x SHARC Processor Hardware Reference for a description of the clock configu-
ration modes.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset.
BOOT_CFG
1–0
I Boot Configuration Select. These pins select the boot mode for the processor. The
BOOT_CFG pins must be valid before reset is asserted. See the
ADSP-2137x SHARC
Processor Hardware Reference
for information about boot modes.
Table 9. Pin Descriptions (Continued)
Name Type
State During
and After
Reset Description