Datasheet

ManualsBrandsANALOG DEVICES ManualsMicrocontrollers, Microprocessors & QuartzesDigital signal processor (DSP) LQFP 208 EP (28x28) 1.2 V 266 MHz

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SHARC Processor

ADSP-21371/ADSP-21375

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SUMMARY

High performance 32-bit/40-bit floating point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory, ADSP-21371—1M bits of on-chip SRAM

and 4M bits of on-chip mask-programmable ROM

On-chip memory, ADSP-21375—0.5M bits of on-chip

SRAM and 2M bits of on-chip mask-programmable ROM

Code compatible with all other members of the SHARC family

The ADSP-21371/ADSP-21375 processors are available with a

200/266 MHz core instruction rate with unique audiocen-

tric peripherals such as the digital applications interface,

S/PDIF transceiver, serial ports, precision clock generators,

and more. For complete ordering information, see Order-

ing Guide on Page 56.

DEDICATED AUDIO COMPONENTS

ADSP-21371—S/PDIF-compatible digital audio

receiver/transmitter

ADSP-21371—8 dual data line serial ports that operate at up

to 33 Mbps on each data line — each has a clock, frame

sync, and two data lines that can be configured as either a

receiver or transmitter pair

16 PWM outputs configured as four groups of four outputs

ROM-based security features include

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Available in a 208-lead LQFP_EP package

Figure 1. Functional Block Diagram

Internal Memory I/F

Block 0

RAM/ROM

B0D

64-BIT

Instruction

Cache

5 stage

Sequencer

PEx PEy

PMD 64-BIT

IODO 32-BIT

EPD BUS 48-BIT

Core Bus

Cross Bar

DAI Routing/Pins

PCG

DPI Routing/Pins

SPI/B UART

Block 1

RAM/ROM

Block 2

RAM

Block 3

RAM

AMI

SDRAM

External Port Pin MUX

TIMER

SPORT

PWM

DAG1/2 Timer

IDP/

PDAP

TWI

IOD0 BUS

MTM/

PCG

PERIPHERAL BUS

32-BIT

CORE

FLAGS

FLAGx/IRQx/

TMREXP

JTAG

Internal Memory

DMD 64-BIT

PMD 64-BIT

CORE

FLAGS

IOD1

32-BIT

PERIPHERAL BUS

B1D

64-BIT

B2D

64-BIT

B3D

64-BIT

DPI Peripherals DAI Peripherals Peripherals

External

Port

SIMD Core

DTCP

S/PDIF

Tx/Rx

DMD 64-BIT

Summary of content (56 pages)

PAGE 1
SHARC Processor ADSP-21371/ADSP-21375 SUMMARY DEDICATED AUDIO COMPONENTS High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory, ADSP-21371—1M bits of on-chip SRAM and 4M bits of on-chip mask-programmable ROM On-chip memory, ADSP-21375—0.
PAGE 2
ADSP-21371/ADSP-21375 TABLE OF CONTENTS Summary ............................................................... 1 Package Information ............................................ 18 Dedicated Audio Components ................................. 1 Maximum Power Dissipation ................................. 18 General Description ................................................. 3 Absolute Maximum Ratings ................................... 18 SHARC Family Core Architecture ............................
PAGE 3
ADSP-21371/ADSP-21375 GENERAL DESCRIPTION The ADSP-21371/ADSP-21375 SHARC® processors are members of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processors are source code compatible with the ADSP-2126x, ADSP-2136x, and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode.
PAGE 4
ADSP-21371/ADSP-21375 SHARC FAMILY CORE ARCHITECTURE Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements.
PAGE 5
ADSP-21371/ADSP-21375 Data Register File Each processing element contains a general-purpose data register file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the SHARC’s enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15.
PAGE 6
ADSP-21371/ADSP-21375 Table 3.
PAGE 7
ADSP-21371/ADSP-21375 Table 4.
PAGE 8
ADSP-21371/ADSP-21375 SHARC processor are 48 bits wide, instruction throughput when executing code from external SDRAM memory is 2 instructions every 3 SDCLK (peripheral) clock cycles over a 32bit wide external port, and 2 instructions every 6 SDCLK clock cycles over a 16-bit external port. Non SDRAM external memory address space is shown in Table 6. Table 6.
PAGE 9
ADSP-21371/ADSP-21375 Serial ports operate in five modes: • Standard DSP serial mode • Multichannel (TDM) mode with support for packed I2S mode but data is sent to the FIFO as 32-bit words (that is, one-half of a frame at a time). The processor supports 24- and 32-bit I2S, 24and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justified formats.
PAGE 10
ADSP-21371/ADSP-21375 DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The UART port’s baud rate, serial data format, error code generation and status, and interrupts are programmable. The port: • Supports bit rates ranging from (fPCLK/1,048,576) to (fPCLK/16) bits per second. • Supports data formats from 7 to 12 bits per frame.
PAGE 11
ADSP-21371/ADSP-21375 Power Supplies EZ-KIT Lite Evaluation Kits The processors have separate power supply connections for the internal (VDDINT), and external (VDDEXT) power supplies. The internal supplies must meet the 1.2 V requirement. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply. For a cost-effective way to learn more about developing with Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits.
PAGE 12
ADSP-21371/ADSP-21375 Designing an Emulator-Compatible DSP Board (Target) For embedded system test and debug, Analog Devices provides a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit emulation is facilitated by use of this JTAG interface. The emulator accesses the processor’s internal features via the processor’s TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers.
PAGE 13
ADSP-21371/ADSP-21375 PIN FUNCTION DESCRIPTIONS The following symbols appear in the Type column of Table 9: A = asynchronous, I = input, O = output, S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor. Table 9. Pin Descriptions State During and After Reset Description Name Type ADDR23–0 O/T (pu) Pulled high/ driven low External Address. The processor outputs addresses for external memory and peripherals on these pins.
PAGE 14
ADSP-21371/ADSP-21375 Table 9. Pin Descriptions (Continued) State During and After Reset Description Name Type SDCKE O/T (pu) Pulled high/ driven high SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK signal. For details, see the data sheet supplied with the SDRAM device. SDA10 O/T (pu) Pulled high/ driven low SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a nonSDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.
PAGE 15
ADSP-21371/ADSP-21375 Table 9. Pin Descriptions (Continued) 1 State During and After Reset Name Type Description RESET I Processor Reset. Resets the processor to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up. XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.
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ADSP-21371/ADSP-21375 ADSP-21371/ADSP-21375 SPECIFICATIONS OPERATING CONDITIONS 1.
PAGE 17
ADSP-21371/ADSP-21375 ELECTRICAL CHARACTERISTICS 1.0 V, 200 MHz Parameter1 Description Test Conditions Min VOH2 VOL2 IIH4, 5 IIL4 IILPU5 @ VDDEXT = Min, IOH = –1.0 mA3 @ VDDEXT = Min, IOL = 1.0 mA3 @ VDDEXT = Max, VIN = VDDEXT max @ VDDEXT = Max, VIN = 0 V @ VDDEXT = Max, VIN = 0 V 2.
PAGE 18
ADSP-21371/ADSP-21375 PACKAGE INFORMATION Table 11. Absolute Maximum Ratings (Continued) The information presented in Figure 3 provides details about the package branding for the ADSP-21371/ADSP-21375 processor. For a complete listing of product availability, see Ordering Guide on Page 56. Parameter Load Capacitance Storage Temperature Range Junction Temperature under Bias Rating 200 pF –65C to +150C 125C ESD SENSITIVITY a ESD (electrostatic discharge) sensitive device.
PAGE 19
ADSP-21371/ADSP-21375 Voltage Controlled Oscillator fINPUT = CLKIN when the input divider is disabled or In application designs, the PLL multiplier value should be selected in such a way that the VCO frequency never exceeds fVCO specified in Table 14. fINPUT = CLKIN  2 when the input divider is enabled Note the definitions of the clock periods that are a function of CLKIN and the appropriate ratio control shown in Table 12.
PAGE 20
ADSP-21371/ADSP-21375 Power-Up Sequencing The timing requirements for processor startup are given in Table 13. Note that during power-up, a leakage current of approximately 200 μA may be observed on the RESET pin. This leakage current results from the weak internal pull-up resistor on this pin being enabled during power-up. Table 13.
PAGE 21
ADSP-21371/ADSP-21375 Clock Input Table 14. Clock Input Min Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) tCCLK2 CCLK Period VCO Frequency fVCO 1 2 200 MHz Max 301 151 151 5 200 266 MHz Max Min 22.51 11.251 11.251 100 45 45 6 10 800 100 45 45 6 10 800 3.75 200 Unit ns ns ns ns ns MHz Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in the PMCTL register.
PAGE 22
ADSP-21371/ADSP-21375 Reset Table 15. Reset Parameter Timing Requirements tWRST1 RESET Pulse Width Low tSRST RESET Setup Before CLKIN Low 1 Min Max 4 × tCK 8 Unit ns ns Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). CLKIN tWRST tSRST RESET Figure 8.
PAGE 23
ADSP-21371/ADSP-21375 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP pin). Table 17. Core Timer Parameter Switching Characteristic tWCTIM TMREXP Pulse Width Min Max 4 × tPCLK – 1 Unit ns tWCTIM FLAG3 (TMREXP) Figure 10.
PAGE 24
ADSP-21371/ADSP-21375 Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0 and Timer1 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the specifications provided below are valid at the DPI_P14–1 pins. Table 19. Timer PWM_OUT Timing Parameter Switching Characteristic tPWMO Timer Pulse Width Output Min Max Unit 2 × tPCLK – 2 2 × (231 – 1) × tPCLK ns tPWMO PWM OUTPUTS Figure 12.
PAGE 25
ADSP-21371/ADSP-21375 Pin to Pin Direct Routing (DAI and DPI) For direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O). Table 21. DAI/DPI Pin to Pin Routing Parameter Timing Requirement tDPIO Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid Min Max Unit 1.5 10 ns DAI_Pn DPI_Pn tDPIO DAI_Pm DPI_Pm Figure 14. DAI/DPI Pin to Pin Direct Routing Rev.
PAGE 26
ADSP-21371/ADSP-21375 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available.
PAGE 27
ADSP-21371/ADSP-21375 Flags The timing specifications provided below apply to the FLAG3–0 and DPI_P14–1 pins, and the DATA31–0 pins. See Table 9 on Page 13 for more information on flag use. Table 23. Flags Parameter Timing Requirement DPI_P14–1, DATA31–0, FLAG3–0 IN Pulse Width tFIPW Switching Characteristic tFOPW DPI_P14–1, DATA31–0, FLAG3–0 OUT Pulse Width Min FLAG INPUTS tFIPW FLAG OUTPUTS tFOPW Figure 16. Flags Rev.
PAGE 28
ADSP-21371/ADSP-21375 SDRAM Interface Timing Maximum SDRAM frequency for 1.2 V is 133 MHz SDCLK. Table 24. SDRAM Interface Timing1 Parameter Timing Requirements tSSDAT DATA Setup Before SDCLK DATA Hold After SDCLK tHSDAT Switching Characteristics tSDCLK SDCLK Period tSDCLKH SDCLK Width High tSDCLKL SDCLK Width Low tDCAD Command, ADDR, Data Delay After SDCLK2 Command, ADDR, Data Hold After SDCLK2 tHCAD tDSDAT Data Disable After SDCLK tENSDAT Data Enable After SDCLK 1 2 Min 1.0 V, 200 MHz Max 1.
PAGE 29
ADSP-21371/ADSP-21375 Memory Read—Bus Master Use these specifications for asynchronous interfacing to memories. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. Table 25. Memory Read—Bus Master 1.0 V, 200 MHz Max Parameter Min Timing Requirements tDAD Address, Selects Delay to Data Valid1, 2, 3 W + tSDCLK – 5.12 1, 3 tDRLD RD Low to Data Valid W–3 tSDS Data Setup to RD High 2.
PAGE 30
ADSP-21371/ADSP-21375 ADDR MSx tDARL tRW tDRHA RD tDRLD tSDS tDAD tHDRH DATA tDSAK tDAAK ACK WR Figure 18. Memory Read—Bus Master Rev.
PAGE 31
ADSP-21371/ADSP-21375 Memory Write—Bus Master Use these specifications for asynchronous interfacing to memories. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. Table 26. Memory Write—Bus Master 1.0 V, 200 MHz 1.2 V, 266 MHz Parameter Min Max Min Max Timing Requirements tDAAK ACK Delay from Address, Selects1, 2 tSDCLK – 11 + W tSDCLK – 10.1 + W tDSAK ACK Delay from WR Low 1, 3 W – 7.35 W – 7.
PAGE 32
ADSP-21371/ADSP-21375 ADDR MSx tDWHA tDAWH tDAWL tWW WR tWWR tWDE tDDWH tDATRWH DATA tDSAK tDWHD tDAAK ACK RD Figure 19. Memory Write—Bus Master Rev.
PAGE 33
ADSP-21371/ADSP-21375 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (SCLK) width. Serial port signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 27.
PAGE 34
ADSP-21371/ADSP-21375 Table 28.
PAGE 35
ADSP-21371/ADSP-21375 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE tSCLKIW DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE DAI_P20–1 (SCLK) DAI_P20–1 (SCLK) tDFSI tDFSE tSFSI tHOFSI tHFSI DAI_P20–1 (FS) tSFSE tHFSE tSDRE tHDRE tHOFSE DAI_P20–1 (FS) tSDRI tHDRI DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (DATA CHANNEL A/B) DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE tSCLKIW DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE DAI_P20–1 (SCLK) tSCLKW SAMPLE EDGE DAI_P20–1 (SCLK) tDFSI tDFSE
PAGE 36
ADSP-21371/ADSP-21375 Table 29. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN1 Data Enable from External Transmit SCLK tDDTTE1 Data Disable from External Transmit SCLK 1 tDDTIN Data Enable from Internal Transmit SCLK 1 Min 1.0 V, 200 MHz Max 2 Min 1.2 V, 266 MHz Max 2 11.3 –1 10 –1 Referenced to drive edge.
PAGE 37
ADSP-21371/ADSP-21375 Table 30. Serial Ports—External Late Frame Sync Parameter Min Switching Characteristics tDDTLFSE1 Data Delay from Late External Transmit Frame Sync or External Receive Frame Sync with MCE = 1, MFD = 0 tDDTENFS1 Data Enable for MCE = 1, MFD = 0 0.5 1 1.0 V, 200 MHz Max Min 1.2 V, 266 MHz Max 12.7 10 0.
PAGE 38
ADSP-21371/ADSP-21375 Input Data Port (IDP) The timing requirements for the IDP are given in Table 31. IDP signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 31.
PAGE 39
ADSP-21371/ADSP-21375 Note that the 20-bits of external PDAP data can be provided through the external port DATA31–12 pins. On the ADSP-21375 processors, PDAP can not be multiplexed on the external port (since only DATA15–0). Use the SRU DAI instead. Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 32. PDAP is the parallel mode operation of Channel 0 of the IDP.
PAGE 40
ADSP-21371/ADSP-21375 Pulse-width modulation generator information does not apply to the ADSP-21375. Pulse-Width Modulation Generators (PWM) For the ADSP-21371, the following timing specifications apply when the DATA31–16 pins are configured as PWM. Table 33. Pulse-Width Modulation (PWM) Timing Parameter Switching Characteristics tPWMW PWM Output Pulse Width tPWMP PWM Output Period Min Max Unit tPCLK – 2.5 2 × tPCLK – 2.5 (216 – 2) × tPCLK (216 – 1) × tPCLK ns ns tPWMW PWM OUTPUTS tPWMP Figure 25.
PAGE 41
ADSP-21371/ADSP-21375 output mode) from an LRCLK transition, so that when there are 64 serial clock periods per LRCLK period, the LSB of the data will be right-justified to the next LRCLK transition. S/PDIF Transmitter For the ADSP-21371, serial data input to the S/PDIF transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16-, 18-, 20-, or 24-bits. The following sections provide timing for the transmitter.
PAGE 42
ADSP-21371/ADSP-21375 S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 34. Input signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 34.
PAGE 43
ADSP-21371/ADSP-21375 S/PDIF Receiver Internal Digital PLL Mode For the ADSP-21371, the following section describes timing as it relates to the S/PDIF receiver. In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × Frame Sync clock. The S/PDIF receiver information does not apply to the ADSP-21375. Table 36.
PAGE 44
ADSP-21371/ADSP-21375 SPI Interface—Master The processor contains two SPI ports. Both primary and secondary are available through DPI only. The timing provided in Table 37 and Table 38 applies to both. Table 37.
PAGE 45
ADSP-21371/ADSP-21375 SPI Interface—Slave Table 38.
PAGE 46
ADSP-21371/ADSP-21375 Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing Figure 33 describes UART port receive and transmit operations. The maximum baud rate is PCLK/16 where PCLK = 1/tPCLK. As shown in Figure 33 there is some latency between the generation of internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART. Table 39.
PAGE 47
ADSP-21371/ADSP-21375 TWI Controller Timing Table 40 and Figure 34 provide timing information for the TWI interface. Input signals (SCL, SDA) are routed to the DPI_P14–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins. Table 40. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices1 Parameter fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tSUSTO tBUF tSP 1 SCL Clock Frequency Hold Time (repeated) Start Condition.
PAGE 48
ADSP-21371/ADSP-21375 JTAG Test Access Port and Emulation Table 41.
PAGE 49
ADSP-21371/ADSP-21375 OUTPUT DRIVE CURRENTS CAPACITIVE LOADING Figure 36 shows typical I-V characteristics for the output drivers of the processors. The curves represent the current drive capability of the output drivers as a function of output voltage. Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 37). Figure 41 shows graphically how output delays and holds vary with load capacitance.
PAGE 50
ADSP-21371/ADSP-21375 Values of JB are provided for package comparison and PCB design considerations. Note that the thermal characteristics values provided in Table 42 are modeled values. 10 OUTPUT DELAY OR HOLD (ns) 8 Table 42. Thermal Characteristics for 208-Lead LQFP E_PAD (With Exposed Pad Soldered to PCB) Y = 0.0488X - 1.5923 6 4 2 0 -2 -4 0 50 100 150 200 LOAD CAPACITANCE (pF) Figure 41. Typical Output Delay or Hold vs.
PAGE 51
ADSP-21371/ADSP-21375 208-LEAD LQFP_EP PINOUT Table 43. ADSP-21371, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number) Pin No.
PAGE 52
ADSP-21371/ADSP-21375 Table 43. ADSP-21371, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number) (Continued) Pin No. 45 Signal DATA5 Pin No. 97 Signal ADDR19 Pin No. 149 Signal DAI_P5 (SD1A) Pin No. 201 46 47 48 49 50 51 52 DATA2 DATA3 DATA0 DATA1 VDDEXT GND VDDINT 98 99 100 101 102 103 104 ADDR20 ADDR21 ADDR23 ADDR22 MS1 MS0 VDDINT 150 151 152 153 154 155 156 VDDEXT GND VDDINT GND VDDINT GND VDDINT 202 203 204 205 206 207 208 Rev.
PAGE 53
ADSP-21371/ADSP-21375 Table 44. ADSP-21375, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Signal VDDINT NC NC GND VDDEXT NC NC NC NC GND VDDINT NC NC NC NC NC NC NC NC NC NC VDDINT GND VDDINT GND NC DATA15 DATA14 DATA13 DATA12 VDDEXT GND VDDINT GND DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 VDDEXT GND VDDINT DATA4 Pin No.
PAGE 54
ADSP-21371/ADSP-21375 Table 44. ADSP-21375, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number) (Continued) Pin No. 45 Signal DATA5 Pin No. 97 Signal ADDR19 Pin No. 149 Signal DAI_P5 (SD1A) Pin No. 201 46 47 48 49 50 51 52 DATA2 DATA3 DATA0 DATA1 VDDEXT GND VDDINT 98 99 100 101 102 103 104 ADDR20 ADDR21 ADDR23 ADDR22 MS1 MS0 VDDINT 150 151 152 153 154 155 156 VDDEXT GND VDDINT GND VDDINT GND VDDINT 202 203 204 205 206 207 208 Rev.
PAGE 55
ADSP-21371/ADSP-21375 PACKAGE DIMENSIONS The processors are available in a 208-lead RoHS compliant LQFP_EP package. 0.75 0.60 0.45 1.00 REF 30.20 30.00 SQ 29.80 1.60 MAX 25.50 REF 28.10 28.00 SQ 27.90 8.712 REF 157 208 156 1 157 1 PIN 1 SEATING PLANE TOP VIEW 8.890 REF *EXPOSED PAD (PINS DOWN) 1.45 1.40 1.35 208 156 0.20 0.15 0.09 0.15 0.10 0.05 0.08 COPLANARITY 7° 3.5° 0° BOTTOM VIEW 52 53 VIEW A ROTATED 90° CCW 105 104 (PINS UP) 105 104 VIEW A 52 53 0.
PAGE 56
ADSP-21371/ADSP-21375 AUTOMOTIVE PRODUCTS Some ADSP-21371/ADSP-21375 models are available for automotive applications with controlled manufacturing. Note that this special model may have specifications that differ from the general release models. The automotive grade products shown in Table 45 are available for use in automotive applications. Contact your local ADI account representative or authorized ADI product distributor for specific product ordering information.