Datasheet

ADSP-21371
JTAG Test Access Port and Emulation
Table 41. JTAG Test Access Port and Emulation
Parameter
Timing Requirements
t
TCK
TCK Period
t
STAP
TDI, TMS Setup Before TCK High
t
HTAP
TDI, TMS Hold After TCK High
t
SSYS
1
System Inputs Setup Before TCK High
t
HSYS
1
System Inputs Hold After TCK High
t
TRSTW
TRST Pulse Width
Switching Characteristics
t
DTDO
TDO Delay from TCK Low
t
DSYS
2
System Outputs Delay After TCK Low
Min
t
CK
5
6
7
18
4  t
CK
Max
7
t
CK
/ 2 + 7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
1
System Inputs = AD15–0, CLKCFG1–0, RESET, BOOTCFG1–0, DAI_Px, and FLAG3–0.
2
System Outputs = DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, and ALE.
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
STAP
t
TCK
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS
Figure 33. IEEE 1149.1 JTAG Test Access Port
Rev. 0 | Page 43 of 48 | June 2007