Datasheet

ADSP-21371
SPI Interface—Master
The ADSP-21371 contains two SPI ports. Both primary and sec-
ondary are available through DPI only. The timing provided in
Table 37 and Table 38 applies to both.
Table 37. SPI Interface Protocol
—Master Switching and Timing Specifications
Parameter Min Max Unit
Timing Requirements
t
SSPIDM
Data Input Valid To SPICLK Edge (Data Input Setup Time) 8.2 ns
t
HSPIDM
SPICLK Last Sampling Edge To Data Input Not Valid 2 ns
Switching Characteristics
t
SPICLKM
Serial Clock Cycle 8 × t
PCLK
– 2 ns
t
SPICHM
Serial Clock High Period 4 × t
PCLK
– 2 ns
t
SPICLM
Serial Clock Low Period 4 × t
PCLK
– 2 ns
t
DDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time) 2.5
t
HDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 ns
t
SDSCIM
FLAG3–0IN (SPI device select) Low to First SPICLK Edge 4 × t
PCLK
– 2 ns
t
HDSM
Last SPICLK Edge to FLAG3–0IN High 4 × t
PCLK
– 2 ns
t
SPITDM
Sequential Transfer Delay 4 × t
PCLK
– 1 ns
FLAG3
- 0
(OUTPUT)
SPICLK
(CP = 0)
(OU TPUT)
SPICLK
(CP = 1)
(OU TPUT)
CPHASE = 1
MOSI
(OU TPUT)
MISO
(INPUT)
CPHASE = 0
MOSI
(OU TPUT)
MISO
(INPUT)
LSB
VALID
MSB
VALID
t
SSPIDM
t
HSPIDM
t
HDSPIDM
LSB MSB
t
HSPIDM
t
DDSPIDM
t
SPICHM
t
SPICLM
t
SPICLM
t
SPICL KM
t
SPICHM
t
HDSM
t
SPITDM
t
HDSPIDM
LSB
VALID
LSB MSB
MSB
VALID
t
HSPIDM
t
DDSPIDM
t
SSPIDM
t
SDSCIM
t
SSPIDM
Figure 29. SPI Master Timing
Rev. 0 | Page 39 of 48 | June 2007