Datasheet

ADSP-21367/ADSP-21368/ADSP-21369
Rev. F | Page 47 of 64 | October 2013
Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This TxCLK
input is divided down to generate the biphase clock.
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 38. Oversampling Clock (TxCLK) Switching Characteristics
Parameter Min Max Unit
TxCLK Frequency for TxCLK = 384 × FS Oversampling Ratio × FS <= 1/t
SITXCLK
MHz
TxCLK Frequency for TxCLK = 256 × FS 49.2 MHz
Frame Rate (FS) 192.0 kHz
Table 39. S/PDIF Receiver Internal Digital PLL Mode Timing
Parameter Min Max Unit
Switching Characteristics
t
DFSI
LRCLK Delay After SCLK 5 ns
t
HOFSI
LRCLK Hold After SCLK –2 ns
t
DDTI
Transmit Data Delay After SCLK 5 ns
t
HDTI
Transmit Data Hold After SCLK –2 ns
t
SCLKIW
1
Transmit SCLK Width 40 ns
1
SCLK frequency is 64 × FS where FS = the frequency of LRCLK.
Figure 35. S/PDIF Receiver Internal Digital PLL Mode Timing
DAI_P20–1
(SCLK)
SAMPLE EDGE
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL
A/B)
DRIVE EDGE
t
SCLKIW
t
DFSI
t
HOFSI
t
DDTI
t
HDTI