Datasheet

ADSP-21367/ADSP-21368/ADSP-21369
Rev. F | Page 41 of 64 | October 2013
Pulse-Width Modulation Generators
Sample Rate Converter—Serial Input Port
The SRC input signals SCLK, frame sync (FS), and SDATA are
routed from the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided in Table 35 are valid at the
DAI_P20–1 pins.
Table 34. PWM Timing
Parameter Min Max Unit
Switching Characteristics
t
PWMW
PWM Output Pulse Width t
PCLK
– 2 (2
16
– 2) × t
PCLK
ns
t
PWMP
PWM Output Period 2 × t
PCLK
– 1.5 (2
16
– 1) × t
PCLK
ns
Figure 28. PWM Timing
PWM
OUTPUTS
t
PWMW
t
PWMP
Table 35. SRC, Serial Input Port
Parameter Min Max Unit
Timing Requirements
t
SRCSFS
1
FS Setup Before SCLK Rising Edge 4 ns
t
SRCHFS
1
FS Hold After SCLK Rising Edge 5.5 ns
t
SRCSD
1
SDATA Setup Before SCLK Rising Edge 4 ns
t
SRCHD
1
SDATA Hold After SCLK Rising Edge 5.5 ns
t
SRCCLKW
Clock Width (t
PCLK
× 4) ÷ 2 – 1 ns
t
SRCCLK
Clock Period t
PCLK
× 4 ns
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.