Datasheet

Rev. F | Page 40 of 64 | October 2013
ADSP-21367/ADSP-21368/ADSP-21369
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 33. PDAP is the parallel mode operation of Channel 0 of
the IDP. For details on the operation of the IDP, see the IDP
chapter of the ADSP-21368 SHARC Processor Hardware
Reference. Note that the 20 bits of external PDAP data can be
provided through the external port DATA31–12 pins or the
DAI pins.
Table 33. Parallel Data Acquisition Port (PDAP)
Parameter Min Max Unit
Timing Requirements
t
SPHOLD
1
PDAP_HOLD Setup Before PDAP_CLK Sample Edge 2.5 ns
t
HPHOLD
1
PDAP_HOLD Hold After PDAP_CLK Sample Edge 2.5 ns
t
PDSD
1
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 3.85 ns
t
PDHD
1
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 2.5 ns
t
PDCLKW
Clock Width (t
PCLK
× 4) ÷ 2 – 3 ns
t
PDCLK
Clock Period t
PCLK
× 4 ns
Switching Characteristics
t
PDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × t
PCLK
+ 3 ns
t
PDSTRB
PDAP Strobe Pulse Width 2 × t
PCLK
– 1 ns
1
Data Source pins are DATA31–12, or DAI pins. Source pins for SCLK and FS are: 1) DATA11–10 pins, 2) DAI pins.
Figure 27. PDAP Timing
DAI_P20–1
(PDAP_CLK)
SAMPLE EDGE
DAI_P20–1
(PDAP_HOLD)
DAI_P20–1
(PDAP_STROBE)
t
PDSTRB
t
PDHLDD
t
PDHD
t
PDSD
t
SPHOLD
t
HPHOLD
t
PDCLK
t
PDCLKW
DAI_P20–1/
ADDR23–4
(PDAP_DATA)