Datasheet

ADSP-21367/ADSP-21368/ADSP-21369
Rev. F | Page 39 of 64 | October 2013
Input Data Port
The timing requirements for the IDP are given in Table 32. IDP
signals SCLK, frame sync (FS), and SDATA are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Table 32. IDP
Parameter Min Max Unit
Timing Requirements
t
SISFS
1
FS Setup Before SCLK Rising Edge 4 ns
t
SIHFS
1
FS Hold After SCLK Rising Edge 2.5 ns
t
SISD
1
SDATA Setup Before SCLK Rising Edge 2.5 ns
t
SIHD
1
SDATA Hold After SCLK Rising Edge 2.5 ns
t
IDPCLKW
Clock Width (t
PCLK
× 4) ÷ 2 – 1 ns
t
IDPCLK
Clock Period t
PCLK
× 4 ns
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
Figure 26. IDP Master Timing
DAI_P20–1
(SCLK)
SAMPLE EDGE
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
t
IDPCLK
t
IDPCLKW
t
SISFS
t
SIHFS
t
SIHD
t
SISD