Datasheet

ADSP-21367/ADSP-21368/ADSP-21369
Rev. F | Page 37 of 64 | October 2013
Figure 23. Serial Ports
Figure 24. Enable and Three-State
DRIVE EDGE SAMPLE EDGE
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(FS)
DAI_P20–1
(SCLK)
t
HOFSI
t
HFSI
t
HDRI
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(FS)
DAI_P20–1
(SCLK)
t
HFSI
t
DDTI
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(FS)
DAI_P20–1
(SCLK)
t
HOFSE
t
HOFSI
t
HDTI
t
HFSE
t
HDTE
t
DDTE
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(FS)
DAI_P20–1
(SCLK)
t
HOFSE
t
HFSE
t
HDRE
DATA RECEIVE—EXTERNAL CLOCK
t
SCLKIW
t
DFSI
t
SFSI
t
SDRI
t
SCLKW
t
DFSE
t
SFSE
t
SDRE
t
DFSE
t
SFSE
t
SFSI
t
DFSI
t
SCLKIW
t
SCLKW
DRIVE EDGE
DRIVE EDGE
DRIVE EDGE
t
DDTIN
t
DDTEN
t
DDTTE
DAI_P20–1
(SCLK, INT)
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(SCLK, EXT)
DAI_P20–1
(DATA
CHANNEL A/B)