Datasheet

Rev. F | Page 36 of 64 | October 2013
ADSP-21367/ADSP-21368/ADSP-21369
Table 29. Serial Ports—Internal Clock
Parameter Min Max Unit
Timing Requirements
t
SFSI
1
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
7ns
t
HFSI
1
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
2.5 ns
t
SDRI
1
Receive Data Setup Before SCLK 7 ns
t
HDRI
1
Receive Data Hold After SCLK 2.5 ns
Switching Characteristics
t
DFSI
2
FS Delay After SCLK (Internally Generated FS in Transmit Mode) 4 ns
t
HOFSI
2
FS Hold After SCLK (Internally Generated FS in Transmit Mode) –1.0 ns
t
DFSIR
2
FS Delay After SCLK (Internally Generated FS in Receive Mode) 9.75 ns
t
HOFSIR
2
FS Hold After SCLK (Internally Generated FS in Receive Mode) –1.0 ns
t
DDTI
2
Transmit Data Delay After SCLK 3.25 ns
t
HDTI
2
Transmit Data Hold After SCLK –1.0 ns
t
SCLKIW
3
Transmit or Receive SCLK Width 2 × t
PCLK
– 1.5 2 × t
PCLK
+ 1.5 ns
1
Referenced to the sample edge.
2
Referenced to drive edge.
3
Minimum SPORT divisor register value.
Table 30. Serial Ports—Enable and Three-State
Parameter Min Max Unit
Switching Characteristics
t
DDTEN
1
Data Enable from External Transmit SCLK 2 ns
t
DDTTE
1
Data Disable from External Transmit SCLK 10 ns
t
DDTIN
1
Data Enable from Internal Transmit SCLK –1 ns
1
Referenced to drive edge.
Table 31. Serial Ports—External Late Frame Sync
Parameter Min Max Unit
Switching Characteristics
t
DDTLFSE
1
Data Delay from Late External Transmit FS or External Receive
FS with MCE = 1, MFD = 0
7.75 ns
t
DDTENFS
1
Data Enable for MCE = 1, MFD = 0 0.5 ns
1
The t
DDTLFSE
and t
DDTENFS
parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.