Datasheet

Rev. F | Page 32 of 64 | October 2013
ADSP-21367/ADSP-21368/ADSP-21369
Memory Write
Use these specifications for asynchronous interfacing to memo-
ries. These specifications apply when the processors are the bus
masters, accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD
, WR, and
strobe timing parameters only applies to asynchronous access
mode.
Table 25. Memory Write
Parameter Min Max Unit
Timing Requirements
t
DAAK
ACK Delay from Address, Selects
1, 2
t
SDCLK
– 9.7 + W ns
t
DSAK
ACK Delay from WR Low
1, 3
W – 4.9 ns
Switching Characteristics
t
DAWH
Address, Selects to WR Deasserted
2
t
SDCLK
–3.1+ W ns
t
DAWL
Address, Selects to WR Low
2
t
SDCLK
–2.7 ns
t
WW
WR Pulse Width W – 1.3 ns
t
DDWH
Data Setup Before WR High t
SDCLK
–3.0+ W ns
t
DWHA
Address Hold After WR Deasserted H + 0.15 ns
t
DWHD
Data Hold After WR Deasserted H + 0.02 ns
t
WWR
WR High to WR, RD Low t
SDCLK
–1.5+ H ns
t
DDWR
Data Disable Before RD Low 2t
SDCLK
– 4.11 ns
t
WDE
Data Enabled to WR Low t
SDCLK
– 3.5 ns
W = (number of wait states specified in AMICTLx register) × t
SDCLK
.
H = (number of hold cycles specified in AMICTLx register) × t
SDCLK
.
1
ACK delay/setup: System must meet t
DAAK
, or t
DSAK
, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet t
DAAK
or t
DSAK
.
2
The falling edge of MSx is referenced.
3
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
Figure 20. Memory Write
ACK
DATA
t
DAWH
t
DWHA
t
WWR
t
DATRWH
t
DWHD
t
WW
t
DDWR
t
DDWH
t
DAWL
t
WDE
t
DSAK
t
DAAK
RD
WR
ADDR
MSx