Datasheet

Rev. F | Page 22 of 64 | October 2013
ADSP-21367/ADSP-21368/ADSP-21369
Clock Signals
The processors can use an external clock or a crystal. See the
CLKIN pin description in Table 8 on Page 13. Programs can
configure the processor to use its internal clock generator by
connecting the necessary components to CLKIN and XTAL.
Figure 8 shows the component connections used for a crystal
operating in fundamental mode.
Note that the clock rate is achieved using a 25 MHz crystal and a
PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed
of 400 MHz). To achieve the full core clock rate, programs need
to configure the multiplier bits in the PMCTL register.
Figure 8. 400 MHz Operation (Fundamental Mode Crystal)
C1
22pF
Y1
R1
1M⍀*
XTAL
CLKIN
C2
22pF
25.00 MHz
R2
47⍀*
ADSP-2136x
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS