Datasheet

ADSP-21367/ADSP-21368/ADSP-21369
Rev. F | Page 19 of 64 | October 2013
• The product of CLKIN and PLLM must never exceed f
VCO
(max) in Table 13 if the input divider is enabled
(INDIV = 1).
The VCO frequency is calculated as follows:
f
VCO
= 2  PLLM  f
INPUT
f
CCLK
= (2  PLLM  f
INPUT
)  (2  PLLD)
where:
f
VCO
= VCO output
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = Divider value 1, 2, 4, or 8 based on the PLLD value pro-
grammed on the PMCTL register. During reset this value is 1.
f
INPUT
= Input frequency to the PLL.
f
INPUT
= CLKIN when the input divider is disabled or
f
INPUT
= CLKIN  2 when the input divider is enabled
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in and
Table 11. All of the timing specifications for the ADSP-2136x
peripherals are defined in relation to t
PCLK
. See the peripheral spe-
cific timing section for each peripheral’s timing information.
Figure 5 shows core to CLKIN relationships with external oscil-
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the processor hardware reference.
Table 11. Clock Periods
Timing
Requirements Description
t
CK
CLKIN Clock Period
t
CCLK
Processor Core Clock Period
t
PCLK
Peripheral Clock Period = 2 × t
CCLK
Figure 5. Core Clock and System Clock Relationship to CLKIN
LOOP
FILTER
CLKIN
PCLK
SDCLK
SDRAM
DIVIDER
PMCTL
(PLLBP)
B
Y
P
A
S
S
M
U
X
DIVIDE
BY 2
PMCTL
(SDCKR)
CCLK
B
Y
P
A
S
S
M
U
X
PLL
XTAL
CLKIN
DIVIDER
PLL
MULTIPLIER
BUF
VCO
BUF
PMCTL
(INDIV)
PLL
DIVIDER
CLK_CFGx/PMCTL (2xPLLM)
P
I
N
M
U
X
CLKOUT (TESTONLY)
DELAY OF
4096 CLKIN
CYCLES
CCLK
PCLK
PMCTL
(PLLBP)
PMCTL
(2xPLLD)
f
VCO
f
CCLK
f
INPUT