Datasheet

ADSP-21367/ADSP-21368/ADSP-21369
Rev. F | Page 45 of 64 | October 2013
Figure 33 shows the left-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of SCLK. The MSB is left-justified to an LRCLK
transition with no MSB delay.
S/PDIF Transmitter Input Data Timing
The timing requirements for the input port are given in
Table 37. Input signals SCLK, frame sync (FS), and SDATA are
routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Figure 33. Left-Justified Mode
MSB
LEFT/RIGHT CHANNEL
LSBMSB–1 MSB–2 LSB+2 LSB+1
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
t
LJD
Table 37. S/PDIF Transmitter Input Data Timing
Parameter Min Max Unit
Timing Requirements
t
SISFS
1
FS Setup Before SCLK Rising Edge 3 ns
t
SIHFS
1
FS Hold After SCLK Rising Edge 3 ns
t
SISD
1
SDATA Setup Before SCLK Rising Edge 3 ns
t
SIHD
1
SDATA Hold After SCLK Rising Edge 3 ns
t
SISCLKW
Clock Width 36 ns
t
SISCLK
Clock Period 80 ns
t
SITXCLKW
Transmit Clock Width 9 ns
t
SITXCLK
Transmit Clock Period 20 ns
1
DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.