Datasheet

Rev. F | Page 44 of 64 | October 2013
ADSP-21367/ADSP-21368/ADSP-21369
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left justified, I
2
S, or right justified with word widths of 16, 18, 20,
or 24 bits. The following sections provide timing for the
transmitter.
S/PDIF Transmitter—Serial Input Waveforms
Figure 31 shows the right-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of SCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output
mode) from an LRCLK transition, so that when there are 64
SCLK periods per LRCLK period, the LSB of the data is right-
justified to the next LRCLK transition.
Figure 32 shows the default I
2
S-justified mode. LRCLK is low
for the left channel and high for the right channel. Data is valid
on the rising edge of SCLK. The MSB is left-justified to an
LRCLK transition but with a single SCLK period delay.
Figure 31. Right-Justified Mode
MSB
LEFT/RIGHT CHANNEL
LSB LSBMSB–1 MSB–2 LSB+2 LSB+1
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
t
RJD
Figure 32. I
2
S-Justified Mode
MSB
LEFT/RIGHT CHANNEL
LSBMSB–1 MSB–2 LSB+2 LSB+1
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
t
I2SD