Datasheet

ADSP-21367/ADSP-21368/ADSP-21369
Rev. F | Page 35 of 64 | October 2013
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Serial port signals SCLK, frame sync (FS), data channel A, data
channel B are routed to the DAI_P20–1 pins using the SRU.
Therefore, the timing specifications provided below are valid at
the DAI_P20–1 pins.
Table 28. Serial Ports—External Clock
400 MHz
366 MHz
350 MHz 333 MHz 266 MHz
Parameter Min Max Min Max Min Max Unit
Timing Requirements
t
SFSE
1
FS Setup Before SCLK
(Externally Generated FS in Either
Transmit or Receive Mode)
2.5 2.5 2.5 ns
t
HFSE
1
FS Hold After SCLK
(Externally Generated FS in Either
Transmit or Receive Mode)
2.5 2.5 2.5 ns
t
SDRE
1
Receive Data Setup Before Receive
SCLK
1.9 2.0 2.5 ns
t
HDRE
1
Receive Data Hold After SCLK 2.5 2.5 2.5 ns
t
SCLKW
SCLK Width (t
PCLK
× 4) ÷ 2 – 0.5 (t
PCLK
× 4) ÷ 2 – 0.5 (t
PCLK
× 4) ÷ 2 – 0.5 ns
t
SCLK
SCLK Period t
PCLK
× 4 t
PCLK
× 4 t
PCLK
× 4 ns
Switching Characteristics
t
DFSE
2
FS Delay After SCLK
(Internally Generated FS in Either
Transmit or Receive Mode)
10.25 10.25 10.25 ns
t
HOFSE
2
FS Hold After SCLK
(Internally Generated FS in Either
Transmit or Receive Mode)
222ns
t
DDTE
2
Transmit Data Delay After Transmit
SCLK
7.8 9.6 9.8 ns
t
HDTE
2
Transmit Data Hold After Transmit
SCLK
222ns
1
Referenced to sample edge.
2
Referenced to drive edge.