Datasheet

Rev. F | Page 30 of 64 | October 2013
ADSP-21367/ADSP-21368/ADSP-21369
Memory Read
Use these specifications for asynchronous interfacing to memo-
ries. These specifications apply when the processors are the bus
master accessing external memory space in asynchronous access
mode. Note that timing for ACK, DATA, RD
, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 24. Memory Read
Parameter Min Max Unit
Timing Requirements
t
DAD
Address, Selects Delay to Data Valid
1, 2
W + t
SDCLK
–5.12 ns
t
DRLD
RD Low to Data Valid
2
W – 3.2 ns
t
SDS
Data Setup to RD High 2.5 ns
t
HDRH
Data Hold from RD High
3, 4
0ns
t
DAAK
ACK Delay from Address, Selects
1, 5
t
SDCLK
–9.5 + W ns
t
DSAK
ACK Delay from RD Low
5
W – 7.0 ns
Switching Characteristics
t
DRHA
Address Selects Hold After RD High RH + 0.20 ns
t
DARL
Address Selects to RD Low
1
t
SDCLK
– 3.3 ns
t
RW
RD Pulse Width W – 1.4 ns
t
RWR
RD High to WR, RD Low HI + t
SDCLK
– 0.8 ns
W = (number of wait states specified in AMICTLx register) × t
SDCLK
.
HI =RHC + IC (RHC = number of read hold cycles specified in AMICTLx register) × t
SDCLK
.
IC = (number of idle cycles specified in AMICTLx register) × t
SDCLK
.
H = (number of hold cycles specified in AMICTLx register) × t
SDCLK
.
1
The falling edge of MSx is referenced.
2
The maximum limit of timing requirement values for t
DAD
and t
DRLD
parameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not used.
3
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.
4
Data hold: User must meet t
HDA
or t
HDRH
in asynchronous access mode. See Test Conditions on Page 51 for the calculation of hold times given capacitive and dc loads.
5
ACK delay/setup: User must meet t
DAAK
, or t
DSAK
, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet t
DAAK
or t
DSAK
.