Datasheet

ADSP-21367/ADSP-21368/ADSP-21369
Rev. F | Page 29 of 64 | October 2013
SDRAM Interface Enable/Disable Timing (166 MHz SDCLK)
Table 23. SDRAM Interface Enable/Disable Timing
1
1
For f
CCLK
= 400 MHz (SDCLK ratio = 1:2.5).
Parameter Min Max Unit
Switching Characteristics
t
DSDC
Command Disable After CLKIN Rise 2 × t
PCLK
+ 3 ns
t
ENSDC
Command Enable After CLKIN Rise 4.0 ns
t
DSDCC
SDCLK Disable After CLKIN Rise 8.5 ns
t
ENSDCC
SDCLK Enable After CLKIN Rise 3.8 ns
t
DSDCA
Address Disable After CLKIN Rise 9.2 ns
t
ENSDCA
Address Enable After CLKIN Rise 2 × t
PCLK
– 4 4 × t
PCLK
ns
Figure 18. SDRAM Interface Enable/Disable Timing
t
DSDC
t
DSDCC
t
DSDCA
t
ENSDC
t
ENSDCA
t
ENSDCC
CLKIN
COMMAND
SDCLK
ADDR
COMMAND
SDCLK
ADDR