Datasheet

Rev. F | Page 28 of 64 | October 2013
ADSP-21367/ADSP-21368/ADSP-21369
SDRAM Interface Timing (166 MHz SDCLK)
The 166 MHz access speed is for a single processor. When mul-
tiple ADSP-21368 processors are connected in a shared memory
system, the access speed is 100 MHz.
Table 22. SDRAM Interface Timing
1
366 MHz 350 MHz
All Other Speed
Grades
Parameter Min Max Min Max Min Max Unit
Timing Requirements
t
SSDAT
DATA Setup Before SDCLK 500 500 500 ps
t
HSDAT
DATA Hold After SDCLK 1.23 1.23 1.23 ns
Switching Characteristics
t
SDCLK
SDCLK Period 6.83 7.14 6.0 ns
t
SDCLKH
SDCLK Width High 3 3 2.6 ns
t
SDCLKL
SDCLK Width Low 3 3 2.6 ns
t
DCAD
Command, ADDR, Data Delay After SDCLK
2
4.8 4.8 4.8 ns
t
HCAD
Command, ADDR, Data Hold After SDCLK
2
1.2 1.2 1.2 ns
t
DSDAT
Data Disable After SDCLK 5.3 5.3 5.3 ns
t
ENSDAT
Data Enable After SDCLK 1.3 1.3 1.3 ns
1
The processor needs to be programmed in t
SDCLK
= 2.5  t
CCLK
mode when operated at 350 MHz, 366 MHz, and 400 MHz.
2
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.
Figure 17. SDRAM Interface Timing
SDCLK
DATA (IN)
DATA (OUT)
COMMAND/ADDR
(OUT)
t
SDCLKH
t
SDCLKL
t
HSDAT
t
SSDAT
t
HCAD
t
DCAD
t
ENSDAT
t
DCAD
t
DSDAT
t
HCAD
t
SDCLK