Datasheet

ADSP-21367/ADSP-21368/ADSP-21369
Rev. F | Page 23 of 64 | October 2013
Reset
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0
,
IRQ1
, and IRQ2 interrupts.
Table 14. Reset
Parameter Min Max Unit
Timing Requirements
t
WRST
1
RESET Pulse Width Low 4t
CK
ns
t
SRST
RESET Setup Before CLKIN Low 8 ns
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable
V
DD
and CLKIN (not including start-up time of external clock oscillator).
Figure 9. Reset
CLKIN
RESET
t
SRST
t
WRST
Table 15. Interrupts
Parameter Min Max Unit
Timing Requirement
t
IPW
IRQx Pulse Width 2 × t
PCLK
+2 ns
Figure 10. Interrupts
INTERRUPT
INPUTS
t
IPW