Datasheet

ADSP-21367/ADSP-21368/ADSP-21369
Rev. F | Page 21 of 64 | October 2013
Clock Input
Table 13. Clock Input
Parameter
400 MHz
1
1
Applies to all 400 MHz models. See Ordering Guide on Page 61.
366 MHz
2
2
Applies to all 366 MHz models. See Ordering Guide on Page 61.
350 MHz
3
3
Applies to all 350 MHz models. See Ordering Guide on Page 61.
333 MHz
4
4
Applies to all 333 MHz models. See Ordering Guide on Page 61.
266 MHz
5
5
Applies to all 266 MHz models. See Ordering Guide on Page 61.
UnitMin Max Min Max Min Max Min Max Min Max
Timing Requirements
t
CK
CLKIN Period 15
6
6
Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.
100 16.39
6
100 17.14
6
100 18
6
100 22.5
6
100 ns
t
CKL
CLKIN Width Low 7.5
1
45 8.1
1
45 8.5
1
45 9
1
45 11.25
1
45 ns
t
CKH
CLKIN Width High 7.5
1
45 8.1
1
45 8.5
1
45 9
1
45 11.25
1
45 ns
t
CKRF
CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 3 3 3ns
t
CCLK
7
7
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CCLK
.
CCLK Period 2.5
6
10 2.73
6
10 2.85
6
10 3.0
6
10 3.75
6
10 ns
f
VCO
8
8
See Figure 5 on Page 19 for VCO diagram.
VCO Frequency 100 800 100 800 100 800 100 800 100 600 MHz
t
CKJ
9, 10
9
Actual input jitter should be combined with ac specifications for accurate timing analysis.
10
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
CLKIN Jitter Tolerance –250 +250 –250 +250 –250 +250 –250 +250 –250 +250 ps
Figure 7. Clock Input
CLKIN
t
CK
t
CKL
t
CKH
t
CKJ