Datasheet

Rev. F | Page 20 of 64 | October 2013
ADSP-21367/ADSP-21368/ADSP-21369
Power-Up Sequencing
The timing requirements for processor start-up are given in
Table 12. Note that during power-up, a leakage current of
approximately 200μA may be observed on the RESET
pin if it is
driven low before power up is complete. This leakage current
results from the weak internal pull-up resistor on this pin being
enabled during power-up.
Table 12. Power-Up Sequencing Timing Requirements (Processor Start-up)
Parameter Min Max Unit
Timing Requirements
t
RSTVDD
RESET Low Before V
DDINT
/V
DDEXT
On 0 ns
t
IVDDEVDD
V
DDINT
On Before V
DDEXT
–50 +200 ms
t
CLKVDD
1
CLKIN Valid After V
DDINT
/V
DDEXT
Valid 0 200 ms
t
CLKRST
CLKIN Valid Before RESET Deasserted 10
2
μs
t
PLLRST
PLL Control Setup Before RESET Deasserted 20 μs
Switching Characteristic
t
CORERST
Core Reset Deasserted After RESET Deasserted 4096t
CK
+ 2 t
CCLK
3, 4
1
Valid V
DDINT
/V
DDEXT
assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate
default states at all I/O pins.
4
The 4096 cycle count depends on t
srst
specification in Table 14. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles
maximum.
Figure 6. Power-Up Sequencing
t
RSTVDD
t
CLKVDD
t
CLKRST
t
CORERST
t
PLLRST
V
DDEXT
V
DDINT
CLKIN
CLK_CFG1–0
RESET
RESETOUT
t
IVDDEVDD