SHARC Processor ADSP-21367/ADSP-21368/ADSP-21369 SUMMARY DEDICATED AUDIO COMPONENTS High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—2M bits of on-chip SRAM and 6M bits of on-chip mask programmable ROM Code compatible with all other members of the SHARC family The ADSP-21367/ADSP-21368/ADSP-21369 are available with a 400 MHz core instruction rate with unique audiocentri
ADSP-21367/ADSP-21368/ADSP-21369 TABLE OF CONTENTS Summary ............................................................... 1 ESD Caution ...................................................... 18 Dedicated Audio Components ................................. 1 Maximum Power Dissipation ................................. 18 General Description ................................................. 3 Absolute Maximum Ratings ................................... 18 SHARC Family Core Architecture ..................
ADSP-21367/ADSP-21368/ADSP-21369 GENERAL DESCRIPTION ADSP-21368 Feature ADSP-21369/ ADSP-21369W Table 2. ADSP-2136x Family Features1 (Continued) ADSP-21367 The ADSP-21367/ADSP-21368/ADSP-21369 SHARC® processors are members of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. These processors are source code-compatible with the ADSP-2126x and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode.
ADSP-21367/ADSP-21368/ADSP-21369 The block diagram of the ADSP-21368 on Page 1 also shows the peripheral clock domain (also known as the I/O processor) and contains the following features: • Digital peripheral interface that includes three timers, a 2wire interface, two UARTs, two serial peripheral interfaces (SPI), 2 precision clock generators (PCG) and a flexible signal routing unit (DPI SRU).
ADSP-21367/ADSP-21368/ADSP-21369 SIMD Computational Engine The processors contain two computational processing elements that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register.
ADSP-21367/ADSP-21368/ADSP-21369 processor. The memory architecture, in combination with its separate on-chip buses, allows two data transfers from the core and one from the I/O processor, in a single cycle. Table 3.
ADSP-21367/ADSP-21368/ADSP-21369 FAMILY PERIPHERAL ARCHITECTURE Table 4. External Memory for SDRAM Addresses The ADSP-21367/ADSP-21368/ADSP-21369 family contains a rich set of peripherals that support a wide variety of applications including high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recognition, motor control, imaging, and other applications.
ADSP-21367/ADSP-21368/ADSP-21369 Asynchronous Memory Controller The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with different timing parameters, enabling connection to a wide variety of memory devices including SRAM, ROM, flash, and EPROM, as well as I/O devices that interface with standard memory control lines.
ADSP-21367/ADSP-21368/ADSP-21369 The serial ports also contain frame sync error detection logic where the serial ports detect frame syncs that arrive early (for example, frame syncs that arrive while the transmission/reception of the previous word is occurring). All the serial ports also share one dedicated error interrupt. S/PDIF-Compatible Digital Audio Receiver/Transmitter The S/PDIF receiver/transmitter has no separate DMA channels.
ADSP-21367/ADSP-21368/ADSP-21369 Peripheral Timers Delay Line DMA Three general-purpose timers can generate periodic interrupts and be independently set to operate in one of three modes: The ADSP-21367/ADSP-21368/ADSP-21369 processors provide delay line DMA functionality. This allows processor reads and writes to external delay line buffers (in external memory, SRAM, or SDRAM) with limited core interaction.
ADSP-21367/ADSP-21368/ADSP-21369 EZ-KIT Lite Evaluation Board 100nF 10nF ADSP-213xx 1nF AVDD VDDINT HI-Z FERRITE BEAD CHIP AVSS LOCATE ALL COMPONENTS CLOSE TO AVDD AND AVSS PINS For processor evaluation, Analog Devices provides wide range of EZ-KIT Lite® evaluation boards. Including the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features.
ADSP-21367/ADSP-21368/ADSP-21369 Middleware Packages RELATED SIGNAL CHAINS Analog Devices separately offers middleware add-ins such as real time operating systems, file systems, USB stacks, and TCP/IP stacks.
ADSP-21367/ADSP-21368/ADSP-21369 PIN FUNCTION DESCRIPTIONS The following symbols appear in the Type column of Table 8: A = asynchronous, G = ground, I = input, O = output, O/T = output three-state, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open-drain, (pd) = pull-down resistor, (pu) = pull-up resistor. The ADSP-21367/ADSP-21368/ADSP-21369 SHARC processors use extensive pin multiplexing to achieve a lower pin count.
ADSP-21367/ADSP-21368/ADSP-21369 Table 8. Pin Descriptions (Continued) State During/ After Reset (ID = 00x) Description Name Type SDRAS O/T (pu)1 Pulled high/ driven high SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform. SDCAS O/T (pu)1 Pulled high/ driven high SDRAM Column Address Select. Connect to SDRAM’s CAS pin.
ADSP-21367/ADSP-21368/ADSP-21369 Table 8. Pin Descriptions (Continued) 1 2 State During/ After Reset (ID = 00x) Name Type Description EMU O (O/D, pu) Emulation Status. Must be connected to the ADSP-21367/ADSP-21368/ ADSP-21369 Analog Devices DSP Tools product line of JTAG emulator target board connectors only. CLK_CFG1–0 I Core/CLKIN Ratio Control. These pins set the start-up clock frequency. See the processor hardware reference for a description of the clock configuration modes.
ADSP-21367/ADSP-21368/ADSP-21369 SPECIFICATIONS OPERATING CONDITIONS 366 MHz 350 MHz 400 MHz Parameter1 Description 333 MHz 266 MHz Min Max Min Max Min Max Unit 1.25 1.35 1.235 1.365 1.14 1.26 V VDDINT Internal (Core) Supply Voltage AVDD Analog (PLL) Supply Voltage 1.25 1.35 1.235 1.365 1.14 1.26 V VDDEXT External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 3.13 3.47 V VIH2 High Level Input Voltage @ VDDEXT = Max 2.0 VDDEXT + 0.5 2.0 VDDEXT + 0.5 2.0 VDDEXT + 0.
ADSP-21367/ADSP-21368/ADSP-21369 ELECTRICAL CHARACTERISTICS Parameter Description Test Conditions Min VOH1 Max Unit High Level Output Voltage @ VDDEXT = Min, IOH = –1.0 mA2 2.4 Low Level Output Voltage @ VDDEXT = Min, IOL = 1.0 mA2 0.
ADSP-21367/ADSP-21368/ADSP-21369 PACKAGE INFORMATION Table 10. Absolute Maximum Ratings The information presented in Figure 4 provides details about the package branding for the ADSP-21367/ADSP-21368/ ADSP-21369 processors. For a complete listing of product availability, see Ordering Guide on Page 61.
ADSP-21367/ADSP-21368/ADSP-21369 • The product of CLKIN and PLLM must never exceed fVCO (max) in Table 13 if the input divider is enabled (INDIV = 1). Note the definitions of the clock periods that are a function of CLKIN and the appropriate ratio control shown in and Table 11. All of the timing specifications for the ADSP-2136x peripherals are defined in relation to tPCLK. See the peripheral specific timing section for each peripheral’s timing information.
ADSP-21367/ADSP-21368/ADSP-21369 Power-Up Sequencing driven low before power up is complete. This leakage current results from the weak internal pull-up resistor on this pin being enabled during power-up. The timing requirements for processor start-up are given in Table 12. Note that during power-up, a leakage current of approximately 200μA may be observed on the RESET pin if it is Table 12.
ADSP-21367/ADSP-21368/ADSP-21369 Clock Input Table 13. Clock Input Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) tCCLK7 CCLK Period VCO Frequency fVCO8 tCKJ9, 10 CLKIN Jitter Tolerance 400 MHz1 Min Max 366 MHz2 Min Max 350 MHz3 Min Max 333 MHz4 Min Max 266 MHz5 Min Max 156 7.51 7.51 16.396 8.11 8.11 17.146 8.51 8.51 186 91 91 22.56 11.251 11.251 2.56 100 –250 100 45 45 3 10 800 +250 2.
ADSP-21367/ADSP-21368/ADSP-21369 Clock Signals The processors can use an external clock or a crystal. See the CLKIN pin description in Table 8 on Page 13. Programs can configure the processor to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 8 shows the component connections used for a crystal operating in fundamental mode.
ADSP-21367/ADSP-21368/ADSP-21369 Reset Table 14. Reset Parameter Timing Requirements tWRST1 RESET Pulse Width Low tSRST RESET Setup Before CLKIN Low 1 Min Max Unit 4tCK 8 ns ns Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). CLKIN tWRST tSRST RESET Figure 9.
ADSP-21367/ADSP-21368/ADSP-21369 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP). Table 16. Core Timer Parameter Switching Characteristic tWCTIM TMREXP Pulse Width Min Max 4 × tPCLK – 1 Unit ns tWCTIM FLAG3 (TMREXP) Figure 11. Core Timer Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0, Timer1, and Timer2 in PWM_OUT (pulse-width modulation) mode.
ADSP-21367/ADSP-21368/ADSP-21369 Timer WDTH_CAP Timing The following specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the specification provided in Table 18 is valid at the DPI_P14–1 pins. Table 18. Timer Width Capture Timing Parameter Switching Characteristic tPWI Timer Pulse Width Min Max Unit 2 × tPCLK 2 × (231 – 1) × tPCLK ns tPWI TIMER CAPTURE INPUTS Figure 13.
ADSP-21367/ADSP-21368/ADSP-21369 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available.
ADSP-21367/ADSP-21368/ADSP-21369 Flags The timing specifications provided below apply to the FLAG3–0 and DPI_P14–1 pins, and the serial peripheral interface (SPI). See Table 8 on Page 13 for more information on flag use. Table 21. Flags Parameter Timing Requirement FLAG3–0 IN Pulse Width tFIPW Switching Characteristic tFOPW FLAG3–0 OUT Pulse Width Min ns 2 × tPCLK – 1.5 ns tFIPW FLAG OUTPUTS tFOPW Figure 16. Flags | Page 27 of 64 | Unit 2 × tPCLK + 3 FLAG INPUTS Rev.
ADSP-21367/ADSP-21368/ADSP-21369 SDRAM Interface Timing (166 MHz SDCLK) The 166 MHz access speed is for a single processor. When multiple ADSP-21368 processors are connected in a shared memory system, the access speed is 100 MHz. Table 22.
ADSP-21367/ADSP-21368/ADSP-21369 SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Table 23. SDRAM Interface Enable/Disable Timing1 Parameter Switching Characteristics tDSDC Command Disable After CLKIN Rise tENSDC Command Enable After CLKIN Rise tDSDCC SDCLK Disable After CLKIN Rise tENSDCC SDCLK Enable After CLKIN Rise tDSDCA Address Disable After CLKIN Rise tENSDCA Address Enable After CLKIN Rise 1 Min Unit 2 × tPCLK + 3 ns ns ns ns ns ns 4.0 8.5 3.
ADSP-21367/ADSP-21368/ADSP-21369 Memory Read Use these specifications for asynchronous interfacing to memories. These specifications apply when the processors are the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. Table 24.
ADSP-21367/ADSP-21368/ADSP-21369 ADDR MSx tDARL tRW tDRHA RD tDRLD tSDS tDAD tHDRH DATA tRWR tDSAK tDAAK ACK WR Figure 19. Memory Read Rev.
ADSP-21367/ADSP-21368/ADSP-21369 access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode. Memory Write Use these specifications for asynchronous interfacing to memories. These specifications apply when the processors are the bus masters, accessing external memory space in asynchronous Table 25.
ADSP-21367/ADSP-21368/ADSP-21369 Asynchronous Memory Interface (AMI) Enable/Disable Use these specifications for passing bus mastership between ADSP-21368 processors (BRx). Table 26. AMI Enable/Disable Parameter Switching Characteristics tENAMIAC Address/Control Enable After Clock Rise tENAMID Data Enable After Clock Rise tDISAMIAC Address/Control Disable After Clock Rise tDISAMID Data Disable After Clock Rise Min tDISAMIAC tDISAMID ADDR, WR , RD, MS1–0, DATA tENAMIAC tENAMID Figure 21.
ADSP-21367/ADSP-21368/ADSP-21369 Shared Memory Bus Request Use these specifications for passing bus mastership between ADSP-21368 processors (BRx). Table 27. Multiprocessor Bus Request Parameter Timing Requirements tSBRI BRx, Setup Before CLKIN High tHBRI BRx, Hold After CLKIN High Switching Characteristics tDBRO BRx Delay After CLKIN High BRx Hold After CLKIN High tHBRO Min Max 9 0.5 ns ns 9 1.0 CLKIN tDBRO tHBRO BRX(OUT) tSBRI BRX(IN) Figure 22. Shared Memory Bus Request Rev.
ADSP-21367/ADSP-21368/ADSP-21369 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Serial port signals SCLK, frame sync (FS), data channel A, data channel B are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 28.
ADSP-21367/ADSP-21368/ADSP-21369 Table 29.
ADSP-21367/ADSP-21368/ADSP-21369 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE tSCLKIW DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE DAI_P20–1 (SCLK) SAMPLE EDGE tSCLKW DAI_P20–1 (SCLK) tDFSI tDFSE tSFSI tHOFSI tHFSI DAI_P20–1 (FS) tSFSE tHFSE tSDRE tHDRE tHOFSE DAI_P20–1 (FS) tSDRI tHDRI DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (DATA CHANNEL A/B) DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE tSCLKIW DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE DAI_P20–1 (SCLK) tSCLKW SAMPLE EDGE
ADSP-21367/ADSP-21368/ADSP-21369 EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE DAI_P20–1 (SCLK) tHFSE/I tSFSE/I DAI_P20–1 (FS) tDDTE/I tDDTENFS tHDTE/I DAI_P20–1 (DATA CHANNEL A/B) 2ND BIT 1ST BIT tDDTLFSE LATE EXTERNAL TRANSMIT FS DRIVE SAMPLE DRIVE DAI_P20–1 (SCLK) tSFSE/I tHFSE/I DAI_P20–1 (FS) tDDTE/I tDDTENFS tHDTE/I DAI_P20–1 (DATA CHANNEL A/B) 2ND BIT 1ST BIT tDDTLFSE Figure 25.
ADSP-21367/ADSP-21368/ADSP-21369 Input Data Port The timing requirements for the IDP are given in Table 32. IDP signals SCLK, frame sync (FS), and SDATA are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 32.
ADSP-21367/ADSP-21368/ADSP-21369 chapter of the ADSP-21368 SHARC Processor Hardware Reference. Note that the 20 bits of external PDAP data can be provided through the external port DATA31–12 pins or the DAI pins. Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 33. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, see the IDP Table 33.
ADSP-21367/ADSP-21368/ADSP-21369 Pulse-Width Modulation Generators Table 34. PWM Timing Parameter Switching Characteristics tPWMW PWM Output Pulse Width tPWMP PWM Output Period Min Max Unit tPCLK – 2 2 × tPCLK – 1.5 (216 – 2) × tPCLK (216 – 1) × tPCLK ns ns tPWMW PWM OUTPUTS tPWMP Figure 28. PWM Timing Sample Rate Converter—Serial Input Port The SRC input signals SCLK, frame sync (FS), and SDATA are routed from the DAI_P20–1 pins using the SRU.
ADSP-21367/ADSP-21368/ADSP-21369 SAMPLE EDGE DAI_P20–1 (SCLK) tSRCCLK tSRCCLKW tSRCSFS tSRCHFS DAI_P20–1 (FS) tSRCSD tSRCHD DAI_P20–1 (SDATA) Figure 29. SRC Serial Input Port Timing Rev.
ADSP-21367/ADSP-21368/ADSP-21369 and delay specification with regard to SCLK. Note that SCLK rising edge is the sampling edge and the falling edge is the drive edge. Sample Rate Converter—Serial Output Port For the serial output port, the frame-sync is an input and it should meet setup and hold times with regard to SCLK on the output port. The serial data output, SDATA, has a hold time Table 36.
ADSP-21367/ADSP-21368/ADSP-21369 S/PDIF Transmitter S/PDIF Transmitter—Serial Input Waveforms Serial data input to the S/PDIF transmitter can be formatted as left justified, I2S, or right justified with word widths of 16, 18, 20, or 24 bits. The following sections provide timing for the transmitter. Figure 31 shows the right-justified mode. LRCLK is high for the left channel and low for the right channel. Data is valid on the rising edge of SCLK.
ADSP-21367/ADSP-21368/ADSP-21369 Figure 33 shows the left-justified mode. LRCLK is high for the left channel and low for the right channel. Data is valid on the rising edge of SCLK. The MSB is left-justified to an LRCLK transition with no MSB delay. DAI_P20–1 FS LEFT/RIGHT CHANNEL DAI_P20–1 SCLK tLJD DAI_P20–1 SDATA MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB Figure 33. Left-Justified Mode S/PDIF Transmitter Input Data Timing The timing requirements for the input port are given in Table 37.
ADSP-21367/ADSP-21368/ADSP-21369 SAMPLE EDGE tSITXCLKW tSITXCLK DAI_P20–1 (TxCLK) tSISCLK tSISCLKW DAI_P20–1 (SCLK) tSISFS tSIHFS DAI_P20–1 (FS) tSISD tSIHD DAI_P20–1 (SDATA) Figure 34. S/PDIF Transmitter Input Timing Rev.
ADSP-21367/ADSP-21368/ADSP-21369 Oversampling Clock (TxCLK) Switching Characteristics The S/PDIF transmitter has an oversampling clock. This TxCLK input is divided down to generate the biphase clock. Table 38. Oversampling Clock (TxCLK) Switching Characteristics Parameter TxCLK Frequency for TxCLK = 384 × FS TxCLK Frequency for TxCLK = 256 × FS Frame Rate (FS) Min Max Oversampling Ratio × FS <= 1/tSITXCLK 49.2 192.
ADSP-21367/ADSP-21368/ADSP-21369 SPI Interface—Master The processors contain two SPI ports. The primary has dedicated pins and the secondary is available through the DPI. The timing provided in Table 40 and Table 41 on Page 49 applies to both. Table 40.
ADSP-21367/ADSP-21368/ADSP-21369 SPI Interface—Slave Table 41.
ADSP-21367/ADSP-21368/ADSP-21369 JTAG Test Access Port and Emulation Table 42.
ADSP-21367/ADSP-21368/ADSP-21369 OUTPUT DRIVE CURRENTS TEST CONDITIONS Figure 39 shows typical I-V characteristics for the output drivers and Figure 40 shows typical I-V characteristics for the SDCLK output drivers. The curves represent the current drive capability of the output drivers as a function of output voltage. The ac signal specifications (timing parameters) appear in Table 14 on Page 23 through Table 42 on Page 50. These include output disable time, output enable time, and capacitive loading.
ADSP-21367/ADSP-21368/ADSP-21369 12 10 RISE RISE 8 RISE AND FALL TIMES (ns) RISE AND FALL TIMES (ns) 10 FALL y = 0.049x + 1.5105 8 6 y = 0.0482x + 1.4604 4 2 0 y = 0.0372x + 0.228 6 FALL 4 y = 0.0277x + 0.369 2 0 0 50 100 150 200 250 0 50 LOAD CAPACITANCE (pF) 100 150 200 250 LOAD CAPACITANCE (pF) Figure 43. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Min) Figure 45. SDCLK Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Min) 12 10 RISE y = 0.0467x + 1.
ADSP-21367/ADSP-21368/ADSP-21369 To determine the junction temperature of the device while on the application PCB, use: 10 T J = T TOP + JT P D OUTPUT DELAY OR HOLD (ns) 8 where: 6 y = 0.0488x - 1.5923 TJ = junction temperature (C) 4 TTOP = case temperature (C) measured at the top center of the package 2 JT = junction-to-top (of package) characterization parameter is 0 the typical value from Table 43 and Table 44.
ADSP-21367/ADSP-21368/ADSP-21369 256-BALL BGA_ED PINOUT The following table shows the ADSP-2136x’s pin names and their default function after reset (in parentheses). Table 45. 256-Ball BGA_ED Pin Assignment (Numerically by Ball Number) Ball No.
ADSP-21367/ADSP-21368/ADSP-21369 Table 45. 256-Ball BGA_ED Pin Assignment (Numerically by Ball Number) (Continued) Ball No. N01 N02 N03 N04 N17 N18 N19 N20 U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 1 2 Signal RD SDCLK0 GND VDDEXT GND GND DATA11 DATA10 MS0 MS1 VDDINT GND VDDEXT GND VDDEXT VDDINT VDDEXT GND VDDEXT VDDINT VDDEXT VDDEXT VDDINT VDDEXT VDDINT VDDINT DATA0 DATA2 Ball No.
ADSP-21367/ADSP-21368/ADSP-21369 Figure 49 shows the bottom view of the BGA_ED ball configuration. Figure 50 shows the top view of the BGA_ED ball configuration. 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 2 1 1 8 7 10 9 12 11 14 13 16 15 18 17 20 19 A B C D E F G H J TOP VIEW KEY I/O SIGNALS 6 5 A B C D E F G H J K L M N P R T U V W Y BOTTOM VIEW VDDINT 4 3 K L M N P R T U V W Y KEY VDDEXT GND AVDD AVSS VDDINT NO CONNECT I/O SIGNALS Figure 49.
ADSP-21367/ADSP-21368/ADSP-21369 208-LEAD LQFP_EP PINOUT The following table shows the ADSP-2136x’s pin names and their default function after reset (in parentheses). Table 46. 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number) Lead No.
ADSP-21367/ADSP-21368/ADSP-21369 Table 46. 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number) (Continued) Lead No. 40 41 42 Signal DATA6 VDDEXT GND Lead No. 82 83 84 Signal GND CLKIN XTAL Lead No. 124 125 126 Rev. F Signal FLAG0 DAI_P20 (SFS5) GND | Page 58 of 64 | Lead No. 166 167 168 Signal GND VDDINT TMS October 2013 Lead No.
ADSP-21367/ADSP-21368/ADSP-21369 PACKAGE DIMENSIONS The ADSP-21367/ADSP-21368/ADSP-21369 processors are available in 256-ball RoHS compliant and leaded BGA_ED, and 208-lead RoHS compliant LQFP_EP packages. 0.75 0.60 0.45 1.00 REF 30.20 30.00 SQ 29.80 1.60 MAX 25.50 REF 28.10 28.00 SQ 27.90 8.712 REF 157 208 156 1 157 208 156 1 PIN 1 SEATING PLANE TOP VIEW 1.45 1.40 1.35 8.890 REF EXPOSED PAD (PINS DOWN) 0.20 0.15 0.09 7° 3.
ADSP-21367/ADSP-21368/ADSP-21369 A1 CORNER INDEX AREA 27.00 BSC SQ 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y BALL A1 INDICATOR 24.13 BSC SQ TOP VIEW BOTTOM VIEW 1.27 BSC DETAIL A 1.00 0.80 0.60 DETAIL A 1.70 MAX 0.70 0.60 0.50 0.10 MIN 0.90 0.75 0.60 BALL DIAMETER 0.25 MIN (4 ) COPLANARITY 0.20 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-192-BAL-2 Figure 52.
ADSP-21367/ADSP-21368/ADSP-21369 AUTOMOTIVE PRODUCTS An ADSP-21369 model is available for automotive applications with controlled manufacturing. Note that this special model may have specifications that differ from the general release models. The automotive grade product shown in Table 48 is available for use in automotive applications. Contact your local ADI account representative or authorized ADI product distributor for specific product ordering information.
ADSP-21367/ADSP-21368/ADSP-21369 Rev.
ADSP-21367/ADSP-21368/ADSP-21369 Rev.
ADSP-21367/ADSP-21368/ADSP-21369 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05267-0-10/13(F) Rev.
