Datasheet
Table Of Contents
- Summary
- Dedicated Audio Components
- Table of Contents
- Revision History
- General Description
- SHARC Family Core Architecture
- SIMD Computational Engine
- Independent, Parallel Computation Units
- Data Register File
- Context Switch
- Universal Registers
- Timer
- Single-Cycle Fetch of Instruction and Four Operands
- Instruction Cache
- Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- Flexible Instruction Set
- On-Chip Memory
- On-Chip Memory Bandwidth
- ROM-Based Security
- Family Peripheral Architecture
- I/O Processor Features
- System Design
- Development Tools
- Additional Information
- Related Signal Chains
- SHARC Family Core Architecture
- Pin Function Descriptions
- Specifications
- Operating Conditions
- Electrical Characteristics
- Package Information
- ESD Caution
- Maximum Power Dissipation
- Absolute Maximum Ratings
- Timing Specifications
- Core Clock Requirements
- Power-Up Sequencing
- Clock Input
- Clock Signals
- Reset
- Interrupts
- Core Timer
- Timer PWM_OUT Cycle Timing
- Timer WDTH_CAP Timing
- DAI Pin to Pin Direct Routing
- Precision Clock Generator (Direct Pin Routing)
- Flags
- Memory Read—Parallel Port
- Memory Write—Parallel Port
- Serial Ports
- Input Data Port (IDP)
- Parallel Data Acquisition Port (PDAP)
- Pulse-Width Modulation Generators
- Sample Rate Converter—Serial Input Port
- Sample Rate Converter—Serial Output Port
- S/PDIF Transmitter
- S/PDIF Receiver
- SPI Interface—Master
- SPI Interface—Slave
- JTAG Test Access Port and Emulation
- Output Drive Currents
- Test Conditions
- Capacitive Loading
- Thermal Characteristics
- 144-Lead LQFP_EP Pin Configurations
- 136-Ball BGA Pin Configurations
- Package Dimensions
- Automotive Products
- Ordering Guide
Rev. J | Page 56 of 60 | July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
ORDERING GUIDE
Model
1
1
Z = RoHS compliant part.
Notes
Temperature
Range
2
2
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 14 for junction temperature (T
J
)
specification which is the only temperature specification.
Instruction
Rate
On-Chip
SRAM ROM
Package
Description
Package
Option
ADSP-21363KBC-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1
ADSP-21363KBCZ-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1
ADSP-21363KSWZ-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1
ADSP-21363BBC-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1
ADSP-21363BBCZ-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1
ADSP-21363BSWZ-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1
ADSP-21363YSWZ-2AA
3
3
License from Dolby Laboratories, Inc., and Digital Theater Systems (DTS) required for these products.
–40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1
ADSP-21364KBCZ-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1
ADSP-21364KSWZ-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1
ADSP-21364BBCZ-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1
ADSP-21364BSWZ-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1
ADSP-21364YSWZ-2AA –40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1
ADSP-21366KBCZ-1AR
3,
4,
5
4
Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at
www.analog.com/sharc.
5
R = Tape and reel.
0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1
ADSP-21366KBCZ-1AA
3,
4
0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1
ADSP-21366KSWZ-1AA
3,
4
0°C to +70°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1