Datasheet
Table Of Contents
- Summary
- Dedicated Audio Components
- Table of Contents
- Revision History
- General Description
- SHARC Family Core Architecture
- SIMD Computational Engine
- Independent, Parallel Computation Units
- Data Register File
- Context Switch
- Universal Registers
- Timer
- Single-Cycle Fetch of Instruction and Four Operands
- Instruction Cache
- Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- Flexible Instruction Set
- On-Chip Memory
- On-Chip Memory Bandwidth
- ROM-Based Security
- Family Peripheral Architecture
- I/O Processor Features
- System Design
- Development Tools
- Additional Information
- Related Signal Chains
- SHARC Family Core Architecture
- Pin Function Descriptions
- Specifications
- Operating Conditions
- Electrical Characteristics
- Package Information
- ESD Caution
- Maximum Power Dissipation
- Absolute Maximum Ratings
- Timing Specifications
- Core Clock Requirements
- Power-Up Sequencing
- Clock Input
- Clock Signals
- Reset
- Interrupts
- Core Timer
- Timer PWM_OUT Cycle Timing
- Timer WDTH_CAP Timing
- DAI Pin to Pin Direct Routing
- Precision Clock Generator (Direct Pin Routing)
- Flags
- Memory Read—Parallel Port
- Memory Write—Parallel Port
- Serial Ports
- Input Data Port (IDP)
- Parallel Data Acquisition Port (PDAP)
- Pulse-Width Modulation Generators
- Sample Rate Converter—Serial Input Port
- Sample Rate Converter—Serial Output Port
- S/PDIF Transmitter
- S/PDIF Receiver
- SPI Interface—Master
- SPI Interface—Slave
- JTAG Test Access Port and Emulation
- Output Drive Currents
- Test Conditions
- Capacitive Loading
- Thermal Characteristics
- 144-Lead LQFP_EP Pin Configurations
- 136-Ball BGA Pin Configurations
- Package Dimensions
- Automotive Products
- Ordering Guide
Rev. J | Page 54 of 60 | July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SURFACE-MOUNT DESIGN
Table 47 is provided as an aid to PCB design. For industry stan-
dard design recommendations, refer to IPC-7351, Generic
Requirements for Surface-Mount Design and Land Pattern
Standard.
Figure 48. 136-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-136-1)
Dimensions shown in millimeters
0.25 MIN
*
0.50
0.45
0.40
1.31
1.21
1.10
1.70 MAX
A
B
C
D
E
F
G
J
H
K
L
M
12
13
14
11
10
8
7
6
3
2
1
95
4
N
P
12.10
12.00 SQ
11.90
10.40
BSC SQ
*
COMPLIANT WITH JEDEC STANDARDS MO-275-GGAA-1
WITH EXCEPTION TO BALL DIAMETER.
COPLANARITY
0.12
BALL DIAMETER
0.80
BSC
DETAIL A
A1 BALL
CORNER
A1 BALL
CORNER
DETAIL A
BOTTOM VIEW
TOP VIEW
SEATING
PLANE
Table 47. BGA Data for Use with Surface-Mount Design
Package Package Ball Attach Type
Package Solder Mask
Opening Package Ball Pad Size
136-Ball CSP_BGA (BC-136-1) Solder Mask Defined 0.40 mm diameter 0.53 mm diameter