Datasheet
Table Of Contents
- Summary
- Dedicated Audio Components
- Table of Contents
- Revision History
- General Description
- SHARC Family Core Architecture
- SIMD Computational Engine
- Independent, Parallel Computation Units
- Data Register File
- Context Switch
- Universal Registers
- Timer
- Single-Cycle Fetch of Instruction and Four Operands
- Instruction Cache
- Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- Flexible Instruction Set
- On-Chip Memory
- On-Chip Memory Bandwidth
- ROM-Based Security
- Family Peripheral Architecture
- I/O Processor Features
- System Design
- Development Tools
- Additional Information
- Related Signal Chains
- SHARC Family Core Architecture
- Pin Function Descriptions
- Specifications
- Operating Conditions
- Electrical Characteristics
- Package Information
- ESD Caution
- Maximum Power Dissipation
- Absolute Maximum Ratings
- Timing Specifications
- Core Clock Requirements
- Power-Up Sequencing
- Clock Input
- Clock Signals
- Reset
- Interrupts
- Core Timer
- Timer PWM_OUT Cycle Timing
- Timer WDTH_CAP Timing
- DAI Pin to Pin Direct Routing
- Precision Clock Generator (Direct Pin Routing)
- Flags
- Memory Read—Parallel Port
- Memory Write—Parallel Port
- Serial Ports
- Input Data Port (IDP)
- Parallel Data Acquisition Port (PDAP)
- Pulse-Width Modulation Generators
- Sample Rate Converter—Serial Input Port
- Sample Rate Converter—Serial Output Port
- S/PDIF Transmitter
- S/PDIF Receiver
- SPI Interface—Master
- SPI Interface—Slave
- JTAG Test Access Port and Emulation
- Output Drive Currents
- Test Conditions
- Capacitive Loading
- Thermal Characteristics
- 144-Lead LQFP_EP Pin Configurations
- 136-Ball BGA Pin Configurations
- Package Dimensions
- Automotive Products
- Ordering Guide
Rev. J | Page 48 of 60 | July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
144-LEAD LQFP_EP PIN CONFIGURATIONS
The following table shows the processor’s pin names and, when
applicable, their default function after reset in parentheses.
Table 45. LQFP_EP Pin Assignments
Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
V
DDINT
1V
DDINT
37 V
DDEXT
73 GND 109
CLK_CFG0 2 GND 38 GND 74 V
DDINT
110
CLK_CFG1 3 RD
39 V
DDINT
75 GND 111
BOOT_CFG0 4 ALE 40 GND 76 V
DDINT
112
BOOT_CFG1 5 AD15 41 DAI_P10 (SD2B) 77 GND 113
GND 6 AD14 42 DAI_P11 (SD3A) 78 V
DDINT
114
V
DDEXT
7 AD13 43 DAI_P12 (SD3B) 79 GND 115
GND 8 GND 44 DAI_P13 (SCLK3) 80 V
DDEXT
116
V
DDINT
9V
DDEXT
45 DAI_P14 (SFS3) 81 GND 117
GND 10 AD12 46 DAI_P15 (SD4A) 82 V
DDINT
118
V
DDINT
11 V
DDINT
47 V
DDINT
83 GND 119
GND 12 GND 48 GND 84 V
DDINT
120
V
DDINT
13 AD11 49 GND 85 RESET 121
GND 14 AD10 50 DAI_P16 (SD4B) 86 SPIDS
122
FLAG0 15 AD9 51 DAI_P17 (SD5A) 87 GND 123
FLAG1 16 AD8 52 DAI_P18 (SD5B) 88 V
DDINT
124
AD7 17 DAI_P1 (SD0A) 53 DAI_P19 (SCLK5) 89 SPICLK 125
GND 18 V
DDINT
54 V
DDINT
90 MISO 126
V
DDINT
19 GND 55 GND 91 MOSI 127
GND 20 DAI_P2 (SD0B) 56 GND 92 GND 128
V
DDEXT
21 DAI_P3 (SCLK0) 57 V
DDEXT
93 V
DDINT
129
GND 22 GND 58 DAI_P20 (SFS5) 94 V
DDEXT
130
V
DDINT
23 V
DDEXT
59 GND 95 A
vdd
131
AD6 24 V
DDINT
60 V
DDINT
96 A
vss
132
AD5 25 GND 61 FLAG2 97 GND 133
AD4 26 DAI_P4 (SFS0) 62 FLAG3 98 RESETOUT
134
V
DDINT
27 DAI_P5 (SD1A) 63 V
DDINT
99 EMU 135
GND 28 DAI_P6 (SD1B) 64 GND 100 TDO 136
AD3 29 DAI_P7 (SCLK1) 65 V
DDINT
101 TDI 137
AD2 30 V
DDINT
66 GND 102 TRST 138
V
DDEXT
31 GND 67 V
DDINT
103 TCK 139
GND 32 V
DDINT
68 GND 104 TMS 140
AD1 33 GND 69 V
DDINT
105 GND 141
AD0 34 DAI_P8 (SFS1) 70 GND 106 CLKIN 142
WR
35 DAI_P9 (SD2A) 71 V
DDINT
107 XTAL 143
V
DDINT
36 V
DDINT
72 V
DDINT
108 V
DDEXT
144
GND 145*
*The ePAD is electrically connected to GND inside the chip (see Figure 43 and Figure 44), therefore connecting the pad to GND is optional.
For better thermal performance the ePAD should be soldered to the board and thermally connected to the GND plane with vias.