Datasheet
Table Of Contents
- Summary
- Dedicated Audio Components
- Table of Contents
- Revision History
- General Description
- SHARC Family Core Architecture
- SIMD Computational Engine
- Independent, Parallel Computation Units
- Data Register File
- Context Switch
- Universal Registers
- Timer
- Single-Cycle Fetch of Instruction and Four Operands
- Instruction Cache
- Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- Flexible Instruction Set
- On-Chip Memory
- On-Chip Memory Bandwidth
- ROM-Based Security
- Family Peripheral Architecture
- I/O Processor Features
- System Design
- Development Tools
- Additional Information
- Related Signal Chains
- SHARC Family Core Architecture
- Pin Function Descriptions
- Specifications
- Operating Conditions
- Electrical Characteristics
- Package Information
- ESD Caution
- Maximum Power Dissipation
- Absolute Maximum Ratings
- Timing Specifications
- Core Clock Requirements
- Power-Up Sequencing
- Clock Input
- Clock Signals
- Reset
- Interrupts
- Core Timer
- Timer PWM_OUT Cycle Timing
- Timer WDTH_CAP Timing
- DAI Pin to Pin Direct Routing
- Precision Clock Generator (Direct Pin Routing)
- Flags
- Memory Read—Parallel Port
- Memory Write—Parallel Port
- Serial Ports
- Input Data Port (IDP)
- Parallel Data Acquisition Port (PDAP)
- Pulse-Width Modulation Generators
- Sample Rate Converter—Serial Input Port
- Sample Rate Converter—Serial Output Port
- S/PDIF Transmitter
- S/PDIF Receiver
- SPI Interface—Master
- SPI Interface—Slave
- JTAG Test Access Port and Emulation
- Output Drive Currents
- Test Conditions
- Capacitive Loading
- Thermal Characteristics
- 144-Lead LQFP_EP Pin Configurations
- 136-Ball BGA Pin Configurations
- Package Dimensions
- Automotive Products
- Ordering Guide
Rev. J | Page 46 of 60 | July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
OUTPUT DRIVE CURRENTS
Figure 37 shows typical I-V characteristics for the output driv-
ers of the processor. The curves represent the current drive
capability of the output drivers as a function of output voltage.
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 12 on Page 20 through Table 41 on Page 45. These include
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 38.
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 39. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 38). Figure 42 shows graphically
how output delays and holds vary with load capacitance. The
graphs of Figure 40, Figure 41, and Figure 42 may not be linear
outside the ranges shown for Typical Output Delay versus Load
Capacitance and Typical Output Rise Time (20% to 80%,
V = Min) versus Load Capacitance.
Figure 37. ADSP-2136x Typical Drive
Figure 38. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 39. Voltage Reference Levels for AC Measurements
SWEEP (V
DDEXT
) VOLTAGE (V)
-
20
0 3.50.5 1.5 2.5
0
-
40
-
30
20
40
-
10
S
O
U
R
C
E
(
V
D
D
E
X
T
)
C
U
R
R
E
N
T
(
m
A
)
V
OL
3.11V, +125°C
3.3V, +25°C
3.47V,
-
45°C
V
OH
30
10
3.11V, +125°C
3.3V, +25°C
3.47V,
-
45°C
1.0 2.0 3.0
TO
OUTPUT
PIN
ȍ
V
LOAD
30pF
1.5V
INPUT
OR
OUTPUT
1.5V
Figure 40. Typical Output Rise/Fall Time
(20% to 80%, V
DDEXT
= Max)
Figure 41. Typical Output Rise/Fall Time
(20% to 80%, V
DDEXT
= Min)
LOAD CAPACITANCE (pF)
8
0
0
100 250
12
4
2
10
6
R
I
S
E
A
N
D
F
A
L
L
T
I
M
E
S
(
n
s
)
20015050
FALL
y = 0.0467x + 1.6323
y = 0.045x + 1.524
RISE
LOAD CAPACITANCE (pF)
12
0 50 100 150 200 250
10
8
6
4
R
I
S
E
A
N
D
F
A
L
L
T
I
M
E
S
(
n
s
)
2
0
RISE
FALL
y = 0.049x + 1.5105
y=0.0482x + 1.4604