Datasheet
Table Of Contents
- Summary
- Dedicated Audio Components
- Table of Contents
- Revision History
- General Description
- SHARC Family Core Architecture
- SIMD Computational Engine
- Independent, Parallel Computation Units
- Data Register File
- Context Switch
- Universal Registers
- Timer
- Single-Cycle Fetch of Instruction and Four Operands
- Instruction Cache
- Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- Flexible Instruction Set
- On-Chip Memory
- On-Chip Memory Bandwidth
- ROM-Based Security
- Family Peripheral Architecture
- I/O Processor Features
- System Design
- Development Tools
- Additional Information
- Related Signal Chains
- SHARC Family Core Architecture
- Pin Function Descriptions
- Specifications
- Operating Conditions
- Electrical Characteristics
- Package Information
- ESD Caution
- Maximum Power Dissipation
- Absolute Maximum Ratings
- Timing Specifications
- Core Clock Requirements
- Power-Up Sequencing
- Clock Input
- Clock Signals
- Reset
- Interrupts
- Core Timer
- Timer PWM_OUT Cycle Timing
- Timer WDTH_CAP Timing
- DAI Pin to Pin Direct Routing
- Precision Clock Generator (Direct Pin Routing)
- Flags
- Memory Read—Parallel Port
- Memory Write—Parallel Port
- Serial Ports
- Input Data Port (IDP)
- Parallel Data Acquisition Port (PDAP)
- Pulse-Width Modulation Generators
- Sample Rate Converter—Serial Input Port
- Sample Rate Converter—Serial Output Port
- S/PDIF Transmitter
- S/PDIF Receiver
- SPI Interface—Master
- SPI Interface—Slave
- JTAG Test Access Port and Emulation
- Output Drive Currents
- Test Conditions
- Capacitive Loading
- Thermal Characteristics
- 144-Lead LQFP_EP Pin Configurations
- 136-Ball BGA Pin Configurations
- Package Dimensions
- Automotive Products
- Ordering Guide
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J | Page 45 of 60 | July 2013
JTAG Test Access Port and Emulation
Table 41. JTAG Test Access Port and Emulation
Parameter Min Max Unit
Timing Requirements
t
TCK
TCK Period t
CK
ns
t
STAP
TDI, TMS Setup Before TCK High 5 ns
t
HTAP
TDI, TMS Hold After TCK High 6 ns
t
SSYS
1
System Inputs Setup Before TCK High 7 ns
t
HSYS
1
System Inputs Hold After TCK High 18 ns
t
TRSTW
TRST Pulse Width 4 × t
CK
ns
Switching Characteristics
t
DTDO
TDO Delay from TCK Low 7 ns
t
DSYS
2
System Outputs Delay After TCK Low t
CK
÷ 2 + 7 ns
1
System Inputs = ADDR15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, and FLAG3–0.
2
System Outputs = MISO, MOSI, SPICLK, DAI_Px, ADDR15–0, RD, WR, FLAG3–0, EMU, and ALE.
Figure 36. IEEE 1149.1 JTAG Test Access Port
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
TCK
t
STAP
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS