Datasheet
Table Of Contents
- Summary
- Dedicated Audio Components
- Table of Contents
- Revision History
- General Description
- SHARC Family Core Architecture
- SIMD Computational Engine
- Independent, Parallel Computation Units
- Data Register File
- Context Switch
- Universal Registers
- Timer
- Single-Cycle Fetch of Instruction and Four Operands
- Instruction Cache
- Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- Flexible Instruction Set
- On-Chip Memory
- On-Chip Memory Bandwidth
- ROM-Based Security
- Family Peripheral Architecture
- I/O Processor Features
- System Design
- Development Tools
- Additional Information
- Related Signal Chains
- SHARC Family Core Architecture
- Pin Function Descriptions
- Specifications
- Operating Conditions
- Electrical Characteristics
- Package Information
- ESD Caution
- Maximum Power Dissipation
- Absolute Maximum Ratings
- Timing Specifications
- Core Clock Requirements
- Power-Up Sequencing
- Clock Input
- Clock Signals
- Reset
- Interrupts
- Core Timer
- Timer PWM_OUT Cycle Timing
- Timer WDTH_CAP Timing
- DAI Pin to Pin Direct Routing
- Precision Clock Generator (Direct Pin Routing)
- Flags
- Memory Read—Parallel Port
- Memory Write—Parallel Port
- Serial Ports
- Input Data Port (IDP)
- Parallel Data Acquisition Port (PDAP)
- Pulse-Width Modulation Generators
- Sample Rate Converter—Serial Input Port
- Sample Rate Converter—Serial Output Port
- S/PDIF Transmitter
- S/PDIF Receiver
- SPI Interface—Master
- SPI Interface—Slave
- JTAG Test Access Port and Emulation
- Output Drive Currents
- Test Conditions
- Capacitive Loading
- Thermal Characteristics
- 144-Lead LQFP_EP Pin Configurations
- 136-Ball BGA Pin Configurations
- Package Dimensions
- Automotive Products
- Ordering Guide
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J | Page 39 of 60 | July 2013
Figure 30 shows the default I
2
S-justified mode. The frame sync
is low for the left channel and high for the right channel. Data is
valid on the rising edge of serial clock. The MSB is left-justified
to the frame sync transition but with a delay.
Figure 31 shows the left-justified mode. The frame sync is high
for the left channel and low for the right channel. Data is valid
on the rising edge of serial clock. The MSB is left-justified to the
frame sync transition with no delay.
Table 34. S/PDIF Transmitter I
2
S Mode
Parameter Nominal Unit
Timing Requirement
t
I2SD
FS to MSB Delay in I
2
S Mode 1 SCLK
Figure 30. I
2
S-Justified Mode
MSB
LEFT/RIGHT CHANNEL
LSBMSB–1 MSB–2 LSB+2 LSB+1
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
t
I2SD
Table 35. S/PDIF Transmitter Left-Justified Mode
Parameter Nominal Unit
Timing Requirement
t
LJD
FS to MSB Delay in Left-Justified Mode 0 SCLK
Figure 31. Left-Justified Mode
MSB
LEFT/RIGHT CHANNEL
LSBMSB–1 MSB–2 LSB+2 LSB+1
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
t
LJD