Datasheet
Table Of Contents
- Summary
- Dedicated Audio Components
- Table of Contents
- Revision History
- General Description
- SHARC Family Core Architecture
- SIMD Computational Engine
- Independent, Parallel Computation Units
- Data Register File
- Context Switch
- Universal Registers
- Timer
- Single-Cycle Fetch of Instruction and Four Operands
- Instruction Cache
- Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- Flexible Instruction Set
- On-Chip Memory
- On-Chip Memory Bandwidth
- ROM-Based Security
- Family Peripheral Architecture
- I/O Processor Features
- System Design
- Development Tools
- Additional Information
- Related Signal Chains
- SHARC Family Core Architecture
- Pin Function Descriptions
- Specifications
- Operating Conditions
- Electrical Characteristics
- Package Information
- ESD Caution
- Maximum Power Dissipation
- Absolute Maximum Ratings
- Timing Specifications
- Core Clock Requirements
- Power-Up Sequencing
- Clock Input
- Clock Signals
- Reset
- Interrupts
- Core Timer
- Timer PWM_OUT Cycle Timing
- Timer WDTH_CAP Timing
- DAI Pin to Pin Direct Routing
- Precision Clock Generator (Direct Pin Routing)
- Flags
- Memory Read—Parallel Port
- Memory Write—Parallel Port
- Serial Ports
- Input Data Port (IDP)
- Parallel Data Acquisition Port (PDAP)
- Pulse-Width Modulation Generators
- Sample Rate Converter—Serial Input Port
- Sample Rate Converter—Serial Output Port
- S/PDIF Transmitter
- S/PDIF Receiver
- SPI Interface—Master
- SPI Interface—Slave
- JTAG Test Access Port and Emulation
- Output Drive Currents
- Test Conditions
- Capacitive Loading
- Thermal Characteristics
- 144-Lead LQFP_EP Pin Configurations
- 136-Ball BGA Pin Configurations
- Package Dimensions
- Automotive Products
- Ordering Guide
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J | Page 37 of 60 | July 2013
Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and should
meet setup and hold times with regard to the serial clock on the
output port. The serial data output has a hold time and delay
specification with regard to serial clock. Note that the serial
clock rising edge is the sampling edge and the falling edge is the
drive edge.
Table 32. SRC, Serial Output Port
K and B Grade Y Grade
Parameter Min Max Max Unit
Timing Requirements
t
SRCSFS
1
Frame Sync Setup Before Serial Clock Rising Edge 3 ns
t
SRCHFS
1
Frame Sync Hold After Serial Clock Rising Edge 3 ns
Switching Characteristics
t
SRCTDD
1
Transmit Data Delay After Serial Clock Falling Edge 10.5 12.5 ns
t
SRCTDH
1
Transmit Data Hold After Serial Clock Falling Edge 2 ns
1
The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be
either CLKIN or any of the DAI pins.
Figure 28. SRC Serial Output Port Timing
DAI_P20–1
(SCLK)
SAMPLE EDGE
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
t
SRCCLK
t
SRCCLKW
t
SRCSFS
t
SRCHFS
t
SRCTDD
t
SRCTDH