Datasheet

Rev. J | Page 34 of 60 | July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 29. PDAP is the parallel mode operation of Channel 0 of
the IDP. For details on the operation of the IDP, refer to the
ADSP-2136x SHARC Processor Hardware Reference, “Input
Data Port” chapter.
Note that the most significant 16 bits of external 20-bit PDAP
data can be provided through either the parallel port AD15–0
pins or the DAI_P20–5 pins. The remaining 4 bits can only be
sourced through DAI_P4–1. The timing below is valid at the
DAI_P20–1 pins or at the AD15–0 pins.
Table 29. Parallel Data Acquisition Port (PDAP)
Parameter Min Unit
Timing Requirements
t
SPCLKEN
1
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 2.5 ns
t
HPCLKEN
1
PDAP_CLKEN Hold After PDAP_CLK Sample Edge 2.5 ns
t
PDSD
1
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 3.0 ns
t
PDHD
1
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 2.5 ns
t
PDCLKW
Clock Width (t
PCLK
× 4) ÷ 2 – 3 ns
t
PDCLK
Clock Period t
PCLK
× 4 ns
Switching Characteristics
t
PDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × t
PCLK
– 1 ns
t
PDSTRB
PDAP Strobe Pulse Width 2 × t
PCLK
– 1.5 ns
1
Data source pins are AD15–0 and DAI_P4–1, or DAI pins. Source pins for serial clock and frame sync are DAI pins.
Figure 25. PDAP Timing
DAI_P20–1
(PDAP_CLK)
SAMPLE EDGE
DAI_P20–1
(PDAP_HOLD)
DAI_P20–1
(PDAP_STROBE)
t
PDSTRB
t
PDHLDD
t
PDHD
t
PDSD
t
SPHOLD
t
HPHOLD
t
PDCLK
t
PDCLKW
DAI_P20–1/
ADDR23–4
(PDAP_DATA)