Datasheet

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J | Page 33 of 60 | July 2013
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 28. IDP
signals are routed to the DAI_P20–1 pins using the SRU. There-
fore, the timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 28. IDP
Parameter Min Unit
Timing Requirements
t
SISFS
1
Frame Sync Setup Before Clock Rising Edge 3 ns
t
SIHFS
1
Frame Sync Hold After Clock Rising Edge 3 ns
t
SISD
1
Data Setup Before Clock Rising Edge 3 ns
t
SIHD
1
Data Hold After Clock Rising Edge 3 ns
t
IDPCLKW
Clock Width (t
PCLK
× 4) ÷ 2 – 1 ns
t
IDPCLK
Clock Period t
PCLK
× 4 ns
1
The data, clock, and frame sync signals can come from any of the DAI pins. Clock and frame sync can also come via the PCGs or SPORTs. The PCG’s input can be either
CLKIN or any of the DAI pins.
Figure 24. IDP Master Timing
DAI_P20–1
(SCLK)
SAMPLE EDGE
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
t
IDPCLK
t
IDPCLKW
t
SISFS
t
SIHFS
t
SIHD
t
SISD