Datasheet
Table Of Contents
- Summary
- Dedicated Audio Components
- Table of Contents
- Revision History
- General Description
- SHARC Family Core Architecture
- SIMD Computational Engine
- Independent, Parallel Computation Units
- Data Register File
- Context Switch
- Universal Registers
- Timer
- Single-Cycle Fetch of Instruction and Four Operands
- Instruction Cache
- Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- Flexible Instruction Set
- On-Chip Memory
- On-Chip Memory Bandwidth
- ROM-Based Security
- Family Peripheral Architecture
- I/O Processor Features
- System Design
- Development Tools
- Additional Information
- Related Signal Chains
- SHARC Family Core Architecture
- Pin Function Descriptions
- Specifications
- Operating Conditions
- Electrical Characteristics
- Package Information
- ESD Caution
- Maximum Power Dissipation
- Absolute Maximum Ratings
- Timing Specifications
- Core Clock Requirements
- Power-Up Sequencing
- Clock Input
- Clock Signals
- Reset
- Interrupts
- Core Timer
- Timer PWM_OUT Cycle Timing
- Timer WDTH_CAP Timing
- DAI Pin to Pin Direct Routing
- Precision Clock Generator (Direct Pin Routing)
- Flags
- Memory Read—Parallel Port
- Memory Write—Parallel Port
- Serial Ports
- Input Data Port (IDP)
- Parallel Data Acquisition Port (PDAP)
- Pulse-Width Modulation Generators
- Sample Rate Converter—Serial Input Port
- Sample Rate Converter—Serial Output Port
- S/PDIF Transmitter
- S/PDIF Receiver
- SPI Interface—Master
- SPI Interface—Slave
- JTAG Test Access Port and Emulation
- Output Drive Currents
- Test Conditions
- Capacitive Loading
- Thermal Characteristics
- 144-Lead LQFP_EP Pin Configurations
- 136-Ball BGA Pin Configurations
- Package Dimensions
- Automotive Products
- Ordering Guide
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J | Page 29 of 60 | July 2013
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync (FS) delay and frame sync setup and
hold, 2) data delay and data setup and hold, and 3) serial clock
(SCLK) width.
Serial port signals are routed to the DAI_P20–1 pins using the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 24. Serial Ports—External Clock
K and B Grade Y Grade
Parameter Min Max Max Unit
Timing Requirements
t
SFSE
1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in Either Transmit or Receive Mode) 2.5 ns
t
HFSE
1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in Either Transmit or Receive Mode) 2.5 ns
t
SDRE
1
Receive Data Setup Before Receive SCLK 2.5 ns
t
HDRE
1
Receive Data Hold After SCLK 2.5 ns
t
SCLKW
SCLK Width (t
PCLK
× 4) ÷ 2 – 2 ns
t
SCLK
SCLK Period t
PCLK
× 4 ns
Switching Characteristics
t
DFSE
2
Frame Sync Delay After SCLK
(Internally Generated Frame Sync in Either Transmit or Receive Mode) 9.5 11 ns
t
HOFSE
2
Frame Sync Hold After SCLK
(Internally Generated Frame Sync in Either Transmit or Receive Mode) 2 ns
t
DDTE
2
Transmit Data Delay After Transmit SCLK 9.5 11 ns
t
HDTE
2
Transmit Data Hold After Transmit SCLK 2 ns
1
Referenced to sample edge.
2
Referenced to drive edge.
Table 25. Serial Ports—Internal Clock
K and B Grade Y Grade
Parameter Min Max Max Unit
Timing Requirements
t
SFSI
1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in Either Transmit or Receive Mode) 7 ns
t
HFSI
1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in Either Transmit or Receive Mode) 2.5 ns
t
SDRI
1
Receive Data Setup Before SCLK 7 ns
t
HDRI
1
Receive Data Hold After SCLK 2.5 ns
Switching Characteristics
t
DFSI
2
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode) 3 3.5 ns
t
HOFSI
2
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) –1.0 ns
t
DFSIR
2
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode) 8 9.5 ns
t
HOFSIR
2
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode) –1.0 ns
t
DDTI
2
Transmit Data Delay After SCLK 3 4.0 ns
t
HDTI
2
Transmit Data Hold After SCLK –1.0 ns
t
SCLKIW
Transmit or Receive SCLK Width 2 × t
PCLK
– 2 2 × t
PCLK
+ 2 2 × t
PCLK
+ 2 ns
1
Referenced to the sample edge.
2
Referenced to drive edge.