Datasheet

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J | Page 19 of 60 | July 2013
Clock Input
Clock Signals
The processor can use an external clock or a crystal. Refer to the
CLKIN pin description in Table 6 on Page 11. The user applica-
tion program can configure the processor to use its internal
clock generator by connecting the necessary components to the
CLKIN and XTAL pins. Figure 8 shows the component connec-
tions used for a fundamental frequency crystal operating in
parallel mode.
Note that the clock rate is achieved using a 16.67 MHz crystal
and a PLL multiplier ratio 16:1. (CCLK:CLKIN achieves a clock
speed of 266.72 MHz.) To achieve the full core clock rate, pro-
grams need to configure the multiplier bits in the
PMCTL register.
Table 11. Clock Input
Parameter
200 MHz
1
1
Applies to all 200 MHz models. See Ordering Guide on Page 56.
333 MHz
2
2
Applies to all 333 MHz models. See Ordering Guide on Page 56.
Unit
Min Max Min Max
Timing Requirements
t
CK
CLKIN Period 30
3
3
Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in the PMCTL register.
100 18 100 ns
t
CKL
CLKIN Width Low 12.5 7.5 ns
t
CKH
CLKIN Width High 12.5 7.5 ns
t
CKRF
CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 ns
t
CCLK
4
4
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CCLK
.
CCLK Period 5.0 10 3.0 10 ns
t
VCO
5
5
See Figure 5 on Page 17 for VCO diagram.
VCO Frequency 200 600 200 800 MHz
t
CKJ
6, 7
6
Actual input jitter should be combined with AC specifications for accurate timing analysis.
7
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
CLKIN Jitter Tolerance –250 +250 –250 +250 ps
Figure 7. Clock Input
CLKIN
t
CK
t
CKL
t
CKH
t
CKJ
Figure 8. Recommended Circuit for Fundamental Mode Crystal Operation
C1
22pF
Y1
R1
1M *
XTAL
CLKIN
C2
22pF
24.576MHz
R2
*
ADSP-2136x
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS.
*TYPICAL VALUES
47Ω
Ω