Datasheet
Table Of Contents
- Summary
- Dedicated Audio Components
- Table of Contents
- Revision History
- General Description
- SHARC Family Core Architecture
- SIMD Computational Engine
- Independent, Parallel Computation Units
- Data Register File
- Context Switch
- Universal Registers
- Timer
- Single-Cycle Fetch of Instruction and Four Operands
- Instruction Cache
- Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- Flexible Instruction Set
- On-Chip Memory
- On-Chip Memory Bandwidth
- ROM-Based Security
- Family Peripheral Architecture
- I/O Processor Features
- System Design
- Development Tools
- Additional Information
- Related Signal Chains
- SHARC Family Core Architecture
- Pin Function Descriptions
- Specifications
- Operating Conditions
- Electrical Characteristics
- Package Information
- ESD Caution
- Maximum Power Dissipation
- Absolute Maximum Ratings
- Timing Specifications
- Core Clock Requirements
- Power-Up Sequencing
- Clock Input
- Clock Signals
- Reset
- Interrupts
- Core Timer
- Timer PWM_OUT Cycle Timing
- Timer WDTH_CAP Timing
- DAI Pin to Pin Direct Routing
- Precision Clock Generator (Direct Pin Routing)
- Flags
- Memory Read—Parallel Port
- Memory Write—Parallel Port
- Serial Ports
- Input Data Port (IDP)
- Parallel Data Acquisition Port (PDAP)
- Pulse-Width Modulation Generators
- Sample Rate Converter—Serial Input Port
- Sample Rate Converter—Serial Output Port
- S/PDIF Transmitter
- S/PDIF Receiver
- SPI Interface—Master
- SPI Interface—Slave
- JTAG Test Access Port and Emulation
- Output Drive Currents
- Test Conditions
- Capacitive Loading
- Thermal Characteristics
- 144-Lead LQFP_EP Pin Configurations
- 136-Ball BGA Pin Configurations
- Package Dimensions
- Automotive Products
- Ordering Guide
Rev. J | Page 14 of 60 | July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SPECIFICATIONS
Specifications are subject to change without notice.
OPERATING CONDITIONS
K Grade B Grade Y Grade
Parameter Description Min Nom Max Min Nom Max Min Nom Max Unit
V
DDINT
Internal (Core) Supply
Voltage
1.14 1.2 1.26 1.14 1.2 1.26 0.95 1.0 1.05 V
A
VDD
Analog (PLL) Supply Voltage 1.14 1.2 1.26 1.14 1.2 1.26 0.95 1.0 1.05 V
V
DDEXT
External (I/O) Supply Voltage 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V
V
IH
1
1
Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, and TRST.
High Level Input Voltage @
V
DDEXT
= Max
2.0 V
DDEXT
+ 0.5 2.0 V
DDEXT
+ 0.5 2.0 V
DDEXT
+ 0.5 V
V
IL
1
Low Level Input Voltage @
V
DDEXT
= Min
–0.5 +0.8 –0.5 +0.8 –0.5 +0.8 V
V
IH_CLKIN
2
2
Applies to input pin CLKIN.
High Level Input Voltage @
V
DDEXT
= Max
1.74 V
DDEXT
+ 0.5 1.74 V
DDEXT
+ 0.5 1.74 V
DDEXT
+ 0.5 V
V
IL_CLKIN
Low Level Input Voltage @
V
DDEXT
= Min
–0.5 +1.19 –0.5 +1.19 –0.5 +1.19 V
T
J
3,
4
3
See Thermal Characteristics on Page 47 for information on thermal specifications.
4
See the Engineer-to-Engineer Note “Estimating Power for the ADSP-21362 SHARC Processors” (EE-277) for further information.
Junction Temperature
136-Ball CSP_BGA
0 +110 –40 +125 –40 +125 °C
T
J
3, 4
Junction Temperature
144-Lead LQFP_EP
0 +110 –40 +125 –40 +125 °C