Datasheet

ADSP-21261
Rev. 0 | Page 7 of 44 | March 2006
Serial Peripheral (Compatible) Interface
Serial peripheral interface is an industry-standard synchronous
serial link, enabling the ADSP-21261 SPI-compatible port to
communicate with other SPI-compatible devices. SPI is an
interface consisting of two data pins, one device select pin, and
one clock pin. It is a full-duplex synchronous serial interface,
supporting both master and slave modes. The SPI port can
operate in a multimaster environment by interfacing with up to
four other SPI-compatible devices, either acting as a master or
slave device. The ADSP-21261 SPI-compatible peripheral
implementation also features programmable baud rates up to
37.5 MHz, clock phases, and polarities. The ADSP-21261 SPI-
compatible port uses open-drain drivers to support a multimas-
ter configuration and to avoid data contention.
Parallel Port
The parallel port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15–0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8- or 16-
bit, the maximum data transfer rate is one-third the core clock
speed. As an example, a clock rate of 200 MHz is equivalent to
66M byte/s, and a clock rate of 150 MHz is equivalent to
50M byte/s.
Figure 3. ADSP-21261 Memory Map
RESERVED
0x0004 2000–0x0005 7FFF
BLOCK 0 ROM (1.5M BIT)
0x0005 8000–0x0002 FFFF
IOP REGISTERS
0x0000 0000–0x0003 FFFF
BLOCK 0 SRAM (0.5 M B IT)
0x0004 0000–0x0004 1FFF
RESERVE D
0x0005 3000–0x0005 FFFF
BLOCK 1 SRAM (0.5 M B IT)
0x0006 0000–0x0006 1FFF
BLOC K 1 ROM (1. 5M BI T)
0x0007 8000–0x0007 DFFF
RESE RVED
0x0007 E000–0x0007 FFFF
RESERVE D
0x0006 2000–0x0007 7FFF
LONG WORD
ADD RESSING
RESERVED
0x0008 4000 - 0x000A FFFF
BLOCK 0 ROM (1 .5M B IT)
2
0x000B 0000–0x00 0B BFFF
IOP REGISTERS
0x0000 0000–0x0003 FFFF
BLOCK 0 SRAM (0.5M BIT)
0x0008 0000–0x0008 3F FF
RESERVED
0x000B C000–0x000B FFFF
BLOCK 1 SRAM (0.5 M B IT)
0x000C 0000–0x000C 3FFF
BLOCK 1 RO M (1.5M BIT )
3
0x000F 0 000–0x000F BFFF
RESERVED
0x000F C000–0x000F FFFF
RESERVED
0x000C 4000–0x000E FFFF
NORMAL WORD
ADDRESSI NG
RESERVED
0x0010 8000–0x0015 FFF F
BLOCK 0 ROM (1.5M BIT )
0x0016 0000–0 x0017 7F FF
IOP REGISTERS
0x0000 0000–0x0003 FFFF
BLOCK 0 SRAM (0.5M BIT)
0x0010 0000–0x0010 7FFF
RESERVED
0x0017 8FFF–0x0017 FFFF
BLOCK 1 SRAM (0.5M BIT)
0x0018 0000–0x0018 7FFF
BL OCK 1 ROM ( 1.5M BIT)
0x001E 0000–0x001F 7FFF
RESERVED
0x0018 8000–0x001D F FF F
SHORT W ORD
ADDRES SING
RESERVED
0x0020 0000–0x00FF FFFF
EXTERN AL DMA
AD DRESS S PACE
1
0x0100 0000–0x02FF FFFF
RESERVED
0x0300 0000–0x3FFF F FFF
EXT ERNAL M EMORY
SP ACE
1
EX TERNAL ME MO RY I S NOT D IRECTL Y
A CCESSIBL E BY T HE CORE. DMA MUS T BE
U SED TO READ O R WR ITE TO THIS ME M O RY
USING THE SPI OR PARALLEL PORT.
2
B LOC K 0 ROM HA S A 48 -BIT ADDRES S RA NGE
(0xA0000–0xA7 FFFF).
3
B LOC K 1 ROM HA S A 48 -BIT ADDRES S RA NGE
(0xE0000–0xE7 F FFF).
INTERNAL MEMORY
SPAC E
RESERVED
0x000