Datasheet
ADSP-21261
Rev. 0 | Page 5 of 44 | March 2006
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each
processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2126x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0–R15 and in PEY as S0–S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21261 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 1 on Page 1). With the ADSP-21261’s separate pro-
gram and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a
single cycle.
Instruction Cache
The ADSP-21261 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
The ADSP-21261’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital
signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the ADSP-21261 contain
sufficient registers to allow the creation of up to 32 circular buff-
ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce over-
head, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
Figure 2. ADSP-21261 System Sample Configuration
DAI
SPORT3
SPO RT2
SP ORT1
SPORT0
SCLK0
SD0A
SF S0
SD0B
SRU
DA I_ P1
DAI_P 2
DAI_P 3
DA I_ P1 8
DA I_ P19
DA I_P 20
DAC
(OP TIONAL)
ADC
(OPTI ONAL)
FS
CLK
SDAT
FS
CLK
SDAT
3
CLOCK
2
2
CLKI N
XTAL
CLK_ CFG 1–0
BOOTCFG1–0
FLAG3– 1
ADDR
PARALLEL
PO RT
RA M , R OM
B OOT ROM
I/O D EVIC E
OE
DA T A
WE
RD
WR
CLKOUT
ALE
AD15 –0
LATCH
RESE T JTAG
6
ADSP-21261
ADDRE SS
DATA
CONTROL
CS
FL A G0
PCGB
PCG A
CLK
FS